AD14060/AD14060L
P in
Type
Function
T CLKy1
I/O
Transm it Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) T CLK
pin has a 50 kΩ internal pull-up resistor.
RCLKy1
I/O
Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 kΩ internal pull-up resistor.
T FSy1
RFSy1
I/O
Transm it Fram e Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
Receive Fram e Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
I/O
FLAGy0
I/O/A
Flag P ins. (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
FLAG1
FLAGy2
IRQy2-0
I/O/A
I/O/A
I/A
Flag P ins. (FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP-
21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be
used to signal external peripherals.
Flag P ins. (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMAR1
DMAR2
DMAG1
DMAG2
LyxCLK
I/A
I/A
O/T
O/T
I/O
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
Link P or t Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)1. Each LyxCLK pin has a 50 kΩ
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.
LyxDAT 3-0
LyxACK
I/O
I/O
I
Lin k P or t D ata (y = SH ARC_A, B, C, D; x = Link Ports 1, 3, 4)1. Each LyxDAT pin has a
50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
Link P or t Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)1. Each LyxACK pin has a
50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
EBOOT A
EP RO M Boot Select. (SHARC_A) When EBOOT A is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOT A is low, the LBOOT A and BMSA inputs determine booting mode
for SH ARC_A. See the following table. T his signal is a system configuration selection which should
be hardwired.
LBOOT A
I
Link Boot. When LBOOT A is high, SHARC_A is configured for link port booting. When LBOOT A is
low, SHARC_A is configured for host processor booting or no booting. See the following table. T his
signal is a system configuration selection which should be hardwired.
BMSA
I/O/T2
Boot Mem or y Select. Output: Used as chip select for boot EPROM devices (when EBOOT A = 1,
LBOOT A = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. T his input is a system configuration selection which should be hardwired.
EBOOT BCD
LBOOT BCD
I
I
EP RO M Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOT BCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOT BCD is low, the
LBOOT BCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. T his signal is a system configuration selection which should be hardwired.
LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOT BCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. T his signal is a system configuration selec-
tion which should be hardwired.
REV. A
–10–
ADI [ ADI ]
