AD14060/AD14060L
P in
Type
Function
BMSBCD
I/O/T2
Boot Mem or y Select. Output: Used as chip select for boot EPROM devices (when EBOOT BCD = 1,
LBOOT BCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low,
indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from
external memory. See table below. T his input is a system configuration selection which should be
hardwired.
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input) Host Processor
1 (Input) Link Port
0 (Input) No Booting. Processor executes from external memory.
0 (Input) Reserved
EPROM (Connect BMS to EPROM chip select)
x (Input) Reserved
T IMEXPy
CLKIN
O
I
Tim er Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted
for four cycles when the timer is enabled and T COUNT decrements to zero.
Clock In. (Common to all SHARCs) External clock input to the AD14060/AD14060L. T he instruction
cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified
frequency.
RESET
T CK
T MS
T DI
I/A
I
Module Reset. (Common to all SHARCs) Resets the AD14060/AD14060L to a known state. T his input
must be asserted (low) at power-up.
Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JT AG boundary
scan.
I/S
I/S
Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. T MS has
a 20 kΩ internal pull-up resistor.
Test D ata Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.
T DI has a 20 kΩ internal pull-up resistor.
T DO
O
Test D ata O utput (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
TRST
I/A
Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the AD14060/AD14060L. TRST has a
20 kΩ internal pull-up resistor.
EMU (O/D)
O
Em ulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target
board connector only.
VDD
P
P ower Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (26 pins).
P ower Supply Retur n. (28 pins).
GND
G
NOT ES
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as depicted in the block diagram.
1LINK PORT S 0, 2 and 5 are connected internally as described earlier in Link Port I/O.
2T hree-statable only in EPROM boot mode (when BMS is an output).
REV. A
–11–
ADI [ ADI ]
