Actel Fusion Mixed-Signal FPGAs
DATAVALID will remain high until a subsequent ADC_START is issued. The DATAVALID goes low on
the rising edge of SYSCLK as shown in Figure 2-82 on page 2-108. The RESULT signals will be kept
constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available
when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The
RESULT is latched and remains unchanged until the next DATAVLAID rising edge.
Intra-Conversion
Performing a conversion during power-up, calibration is possible but should be avoided, since the
performance is not guaranteed, as shown in Table 2-46 on page 2-115. This is described as intra-
conversion.
Injected Conversion
A conversion can be interrupted by another conversion. Before the current conversion is finished, a
second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion
is issued before the current conversion is completed, the current conversion would be dropped and
the ADC would start the second conversion on the rising edge of the SYSCLK. This is known as
injected conversion. Since the ADC is synchronous, the minimum time to issue a second conversion
is two clock cycles of SYSCLK after the previous one.
Timing Diagram
tCAL = 3,840 tADCCLK
*
SYSCLK
tRECCLR
tREMCLR
ADCRESET
tSUTVC tHDTVC
TVC[7:0]
tCK2QCAL
tCK2QCAL
CALIBRATE
Note: *Refer to EQ 2-11 on page 2-104 for the calculation on the period of ADCCLK, tADCCLK
.
Figure 2-81 • Power-Up Calibration Status Signal Timing Diagram
Preliminary v1.7
2-107
ACTEL [ Actel Corporation ]
