Device Architecture
And so, STC will be rounded up to 3 to ensure the minimum conversion time is met. The sample
time, tsample, with an STC of 3, is now equal to 0.36 µs.
The total sample time, using EQ 2-19, can now be summated.
= tsync_read + tsample + tdistrib + tpost-cal + tsync_write = 0.015 µs + 0.36 µs + 1.2 µs + 0.24 µs + 0.015 µs = 1.8
EQ 2-19
The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is listed
as follows:
TVC[7:0]
STC[7:0]
= 1
= 3
= 0x01
= 0x03
MODE[3:0] = b'0100 = 0x4*
*Note that no power-down after every conversion is chosen in this case; however, if the application
is power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any
performance.
Integrated Voltage Reference
The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this
reference voltage was chosen to make the prescaling and postscaling factors for the prescaler
blocks change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V
can be connected between the VAREF and GNDREF pins. The VAREFSEL control pin is used to select
the reference voltage.
Table 2-44 • VAREF Bit Function
Name
Bit
Function
VAREF
0
Reference voltage selection
0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.
1 – Input external voltage reference from VAREF and GNDREF
ADC Operation Description
The ADC can be powered down independently of the FPGA core, as an additional control or for
power-saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls
only the comparators in the ADC.
Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a
calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust
calibration scheme to reduce integrated offset and linearity errors. The offset and linearity errors
of the main capacitor array are compensated for with an 8-bit calibration capacitor array. The
offset/linearity error calibration is carried out in two ways. First, a power-up calibration is carried
out when the ADC comes out of reset. This is initiated by the CALIBRATE output of the Analog
Block macro and is a fixed number of ADC_CLK cycles (3,840 cycles), as shown in Figure 2-81 on
page 2-107. In this mode, the linearity and offset errors of the capacitors are calibrated.
To further compensate for drift and temperature-dependent effects, every conversion is followed
by post-calibration of either the offset or a bit of the main capacitor array. The post-calibration
ensures that, over time and with temperature, the ADC remains consistent.
After both calibration and the setting of the appropriate configurations, as explained above, the
ADC is ready for operation. Setting the ADCSTART signal high for one clock period will initiate the
sample and conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The
status signals SAMPLE and BUSY will show when the ADC is sampling and converting (Figure 2-83
on page 2-108). Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held
the analog signal, SAMPLE will go low. After the entire operation has completed and the analog
signal is converted, BUSY will go low and DATAVALID will go high. This indicates that the digital
result is available on the RESULT[11:0] pins.
2-106
Preliminary v1.7
ACTEL [ Actel Corporation ]
