Actel Fusion Mixed-Signal FPGAs
ADC Description
The Actel Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use
models. Figure 2-80 shows a block diagram of the Fusion ADC.
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Configurable resolution: 8-bit, 10-bit, and 12-bit mode
DNL: 0.6 LSB for 10-bit mode
INL: 0.4 LSB for 10-bit mode
No missing code
Internal VAREF = 2.56 V
Maximum Sample Rate = 600 ksps
Power-up calibration and dynamic calibration after every sample to compensate for
temperature drift over time
CALIBRATE
SAMPLE
BUSY
DATAVALID
VAREF
Analog
STATUS
MUX
32
12
Signals from
Analog Quads
SAR ADC
RESULT
CHNUMBER
SYSCLK
STC
MODE
TVC
ADCCLK
Figure 2-80 • ADC Simplified Block Diagram
ADC Configuration Description
The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after
conversion, and dynamic calibration. This is controlled by MODE[3:0], as defined in Table 2-41.
Table 2-41 • Mode Bits Function
Name
Bits
Function
MODE
3
0 – Internal calibration after every conversion; two ADCCLK cycles are used
after the conversion.
1 – No calibration after every conversion
MODE
MODE
2
0 – Power-down after conversion
1 – No Power-down after conversion
1:0
00 – 10-bit
01 – 12-bit
10 – 8-bit
11 – Unused
Preliminary v1.7
2-103
ACTEL [ Actel Corporation ]
