Device Architecture
The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The
ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed
of the ADCCLK in relationship to SYSCLK, based on EQ 2-11.
tADCCLK = 4 × (1 + TVC) × tSYSCLK
EQ 2-11
TVC: Time Divider Control (0–255)
t
ADCCLK is the period of ADCCLK, and must be between 0.5 MHz and 10 MHz
SYSCLK is the period of SYSCLK
t
Table 2-42 • TVC Bits Function
Name
Bits
Function
TVC
[7:0]
SYSCLK divider control
The frequency of ADCCLK, fADCCLK, must be within 0.5 Hz to 10 MHz.
The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the
ADCSTART signal on a rising edge of SYSCLK. Figure 2-82 on page 2-108 and Figure 2-83 on
page 2-108 show the timing diagram for the ADC.
A conversion is performed in three phases. In the first phase, the analog input voltage is sampled
on the input capacitor. This phase is called sample phase. During the sample phase, the output
signals BUSY and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the
analog signal. The sample time can be controlled by input signals STC[7:0]. The sample time can be
calculated by EQ 2-12. When controlling the sample time for the ADC along with the use of
Prescaler or Current Monitor or Temperature Monitor, the minimum sample time for each must be
obeyed. Refer to the corresponding section and Table 2-43 for further information.
tsample = (2 + STC) × tADCCLK
EQ 2-12
STC: Sample Time Control value (0–255)
tSAMPLE is the sample time
Table 2-43 • STC Bits Function
Name
Bits
Function
STC
[7:0]
Sample time control
Sample time is computed based on the period of ADCCLK.
The second phase is called the distribution phase. During distribution phase, the ADC computes the
equivalent digital value from the value stored in the input capacitor. In this phase, the output
signal SAMPLE goes back to '0', indicating the sample is completed; but the BUSY signal remains
'1', indicating the ADC is still busy for distribution. The distribution time depends strictly on the
number of bits. If the ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed. EQ 2-
13 describes the distribution time.
tdistrib = N × tADCCLK
EQ 2-13
N: Number of bits
The last phase is the post-calibration phase. This is an optional phase. The post-calibration phase
takes two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is
completed. If the post-calibration phase is skipped, then the BUSY signal goes to '0' after
distribution phase. As soon as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating
the digital result is available on the RESULT output signals. DATAVAILD will remain '1' until the next
ADCSTART is asserted. Actel recommends enabling post-calibration to compensate for drift and
temperature-dependent effects. This ensures that the ADC remains consistent over time and with
2-104
Preliminary v1.7
ACTEL [ Actel Corporation ]
