Actel Fusion Mixed-Signal FPGAs
ADC Interface Timing
Table 2-45 • ADC Interface Timing
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Description
Mode Pin Setup Time
Parameter
tSUMODE
–2
0.56
0.26
0.68
0.32
1.58
1.27
0.00
0.67
0.90
0.00
0.75
0.43
1.33
0.63
3.12
0.22
2.53
2.06
2.15
2.41
2.17
2.25
0.00
0.63
4.00
100.00
–1
0.64
0.29
0.77
0.36
1.79
1.45
0.00
0.76
1.03
0.00
0.85
0.49
1.51
0.71
3.55
0.25
2.89
2.35
2.45
2.74
2.48
2.56
0.00
0.72
4.00
100.00
Std.
0.75
0.34
0.90
0.43
2.11
1.71
0.00
0.89
1.21
0.00
1.00
0.57
1.78
0.84
4.17
0.30
3.39
2.76
2.88
3.22
2.91
3.01
0.00
0.84
4.00
100.00
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tHDMODE
Mode Pin Hold Time
tSUTVC
Clock Divide Control (TVC) Setup Time
Clock Divide Control (TVC) Hold Time
Sample Time Control (STC) Setup Time
Sample Time Control (STC) Hold Time
Voltage Reference Select (VAREFSEL) Setup Time
Voltage Reference Select (VAREFSEL) Hold Time
Channel Select (CHNUMBER) Setup Time
Channel Select (CHNUMBER) Hold Time
Start of Conversion (ADCSTART) Setup Time
Start of Conversion (ADCSTART) Hold Time
Busy Clock-to-Q
tHDTVC
tSUSTC
tHDSTC
tSUVAREFSEL
tHDVAREFSEL
tSUCHNUM
tHDCHNUM
tSUADCSTART
tHDADCSTART
tCK2QBUSY
tCK2QCAL
Power-Up Calibration Clock-to-Q
Valid Conversion Result Clock-to-Q
Sample Clock-to-Q
tCK2QVAL
tCK2QSAMPLE
tCK2QRESULT
tCLR2QBUSY
tCLR2QCAL
tCLR2QVAL
tCLR2QSAMPLE
tCLR2QRESULT
tRECCLR
Conversion Result Clock-to-Q
Busy Clear-to-Q
Power-Up Calibration Clear-to-Q
Valid Conversion Result Clear-to-Q
Sample Clear-to-Q
Conversion result Clear-to-Q
Recovery Time of Clear
tREMCLR
Removal Time of Clear
tMPWSYSCLK
tFMAXSYSCLK
Clock Minimum Pulse Width for the ADC
Clock Maximum Frequency for the ADC
Preliminary v1.7
2-109
ACTEL [ Actel Corporation ]
