Device Architecture
tMINSYSCLK
tMPWSYSCLK
SYSCLK
tSUADCSTART tHDADCSTART
ADCSTART
tSUMODE tHDMODE
MODE[3:0]
TVC[7:0]
tSUTVC tHDTVC
tSUSTC tHDSTC
STC[7:0]
VAREF
tSUVAREFSEL tHDVAREFSEL
tSUCHNUM tHDCHNUM
CHNUMBER[7:0]
Figure 2-82 • Input Setup Time
3
tSAMPLE
1
tDATA2START
SYSCLK
tSUADCSTART tHDADCSTART
ADCSTART
BUSY
tCK2QBUSY
tCK2QSAMPLE
SAMPLE
2
tCONV
tCK2QVAL
tCK2QVAL
DATAVALID
ADC_RESULT[11:0]
tCLK2RESULT
1st Sample Result
2nd Sample Result
Notes:
1. Refer to EQ 2-12 on page 2-104 for the calculation on the sample time, tSAMPLE
2. See EQ 2-19 on page 2-106 for calculation on the conversion time, tCONV
.
.
3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period
Figure 2-83 • Standard Conversion Status Signal Timing Diagram
2-108
Preliminary v1.7
ACTEL [ Actel Corporation ]
