欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号5962-0421901QUA的Datasheet PDF文件第60页浏览型号5962-0421901QUA的Datasheet PDF文件第61页浏览型号5962-0421901QUA的Datasheet PDF文件第62页浏览型号5962-0421901QUA的Datasheet PDF文件第63页浏览型号5962-0421901QUA的Datasheet PDF文件第65页浏览型号5962-0421901QUA的Datasheet PDF文件第66页浏览型号5962-0421901QUA的Datasheet PDF文件第67页浏览型号5962-0421901QUA的Datasheet PDF文件第68页  
MIL-PRF-38535K  
APPENDIX A  
A.3.1.3.6 Production lot. A production lot shall consist of devices manufactured on the same production line(s) by  
means of the same production technique, materials, controls, and design. Where a production lot identification is  
terminated upon completion of wafer or substrate processing, or at any later point prior to device sealing, it shall be  
permissible to process more than a single device type in a single production lot provided traceability is maintained by  
assembling devices into inspection lots, as defined herein, at the point where production lot identification is  
terminated.  
A.3.1.3.7 Inspection lot - class level S. An inspection lot for class level S microcircuits shall consist of a single  
device type from a single wafer lot in a single package type and lead finish unless otherwise specified in the QM plan.  
With qualifying activity approval, a maximum of 4 wafer lots may be used to form a class level S inspection lot. All  
devices shall be sealed within a single week. All assembly operations from die mounting through package sealing  
shall be completed within the same 6-week period. Each inspection sublot shall be uniquely identified to maintain  
traceability of that sublot from the wafer lot to the inspection lot (see A.3.4.6 and A.4.3.3).  
A.3.1.3.8 Inspection lot - class level B. A quantity of microcircuits submitted at one time for inspection to determine  
compliance with the requirements and acceptance criteria of the applicable device specification. Each inspection lot  
shall consist of microcircuits of a single device type, in a single package type and lead finish. Each inspection lot  
shall be manufactured on the same production lines through final seal by the same production techniques and sealed  
within the same period not exceeding 6 weeks. Inspection lot identification shall be maintained from the time the  
inspection lot is formed through the time the lot is accepted, and shall be traceable to the production lot(s) from which  
the inspection lot was formed (see A.3.4.6 and A.4.3.3).  
A.3.1.3.9 Inspection sublot - class level S. An inspection sublot for class level S microcircuits shall be a division  
(one wafer lot maximum) of parts in an inspection lot into smaller quantities of parts (see A.4.5.2 herein).  
A.3.1.3.10 Inspection lot split - class level B. A class level B inspection lot split shall be a further division of the  
number of parts in an inspection lot into smaller quantities of parts (see A.4.5.2 herein).  
A.3.1.3.11 Wafer lot. A wafer lot consists of microcircuit wafers formed into a lot at the start of wafer fabrication for  
homogeneous processing as a group, and assigned a unique identifier or code to provide traceability, and maintain  
lot integrity throughout the fabrication process (see A.4.3.3 herein).  
A.3.1.3.12 Package type. A package with a unique case outline (see MIL-STD-1835), configuration, materials  
(including bonding wire and die attach), piece parts (excluding pre-forms which differ only in size), and assembly  
processes.  
A.3.1.3.13 Microcircuit group. Microcircuits which are designed to perform the same type of basic circuit function  
(e.g., for linear: Amplifier, comparator, sense amplifier, regulator, etc.; for digital: Logic gate buffer, flip-flop,  
combinational gate, sequential register/counter) within a given circuit technology (e.g., diode transistor logic (DTL),  
non-Schottky transistor transistor logic (TTL), emitter coupled logic (ECL), Schottky TTL, linear, hybrid, metal oxide  
semiconductor(MOS)) which are designed for the same supply, bias and signal voltages and for input-output  
compatibility and which are fabricated by use of the same basic die construction and metallization; the same die  
attach method; and by use of bonding interconnects of the same size, material and attachment method.  
A.3.1.3.14 Percent defective allowable (PDA). Percent defective allowable is the maximum observed percent  
defective which will permit the lot to be accepted after the specified 100 percent test.  
Delta limit ()  
. The maximum change in a specified parameter reading which will permit a device to be  
A.3.1.3.15  
accepted on the specified test, based on a comparison of the present measurement with a specified previous  
measurement. NOTE: When expressed as a percentage value, it shall be calculated as a proportion of the previous  
measured value.  
50  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 复制成功!