AD9512
Reg.
Addr.
(Hex)
Bit(s)
Name
Description
CLK1 AND CLK2
45
<0>
Clock Select
0: CLK2 Drives Distribution Section.
1: CLK1 Drives Distribution Section (Default).
45
45
45
<1>
CLK1 Power-Down
CLK2 Power-Down
1 = CLK1 Input Is Powered Down (Default = 0b).
1 = CLK2 Input Is Powered Down (Default = 0b).
Not Used.
<2>
<4:3>
45
<5>
All Clock Inputs Power- 1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;
Down
(Default = 0b).
45
<7:6>
Not Used.
46 (47) <7:0>
(48) (49)
Not Used.
DIVIDERS
<3:0> Divider High
OUT0
Number of Clock Cycles Divider Output Stays High.
Number of Clock Cycles Divider Output Stays Low.
Phase Offset (Default = 0000b).
4A
(4C)
(4E)
(50)
(52)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
<7:4> Divider Low
OUT0
4A
(4C)
(4E)
(50)
(52)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
<3:0> Phase Offset
OUT0
4B
(4D)
(4F)
(51)
(53)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
<4>
<5>
Start
OUT0
Selects Start High or Start Low.
(Default = 0b).
4B
(4D)
(4F)
(51)
(53)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Force
Forces Individual Outputs to the State Specified in Start (Above).
This Function Requires That Nosync (Below) Also Be Set (Default = 0b).
4B
OUT0
(4D)
(4F)
(51)
(53)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Nosync
OUT0
<6>
Ignore Chip-Level Sync Signal (Default = 0b).
4B
(4D)
(4F)
(51)
(53)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Rev. A | Page 41 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
