AD9512
REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 17. AD9512 Register Map
Def.
Value
Addr
Bit 0
(Hex)
Parameter
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Long
Instruction
Bit 3
Bit 2
Bit 1
(LSB)
(Hex) Notes
00
Serial
Control Port
Configuration
SDO Inactive
(Bidirectional
Mode)
LSB
First
Soft
Reset
Not Used
10
01 to
33
Not Used
FINE DELAY
ADJUST
Fine
Delays
Bypassed
34
35
36
Delay Bypass 4
Not Used
Ramp Capacitor <5:3>
5-Bit Fine Delay <5:1>
Not Used
Bypass
01
00
Bypass
Delay
Delay
Full-Scale 4
Not Used
Not Used
Ramp Current <2:0>
Max. Delay
Full-Scale
Delay Fine
Adjust 4
Not Used 00
Min. Delay
Value
37, 38,
39, 3A,
3B, 3C
OUTPUTS
3D
3E
3F
40
LVPECL OUT0
Not Used
Output Level
<3:2>
Power-Down
08
08
08
02
ON
<1:0>
LVPECL OUT1
LVPECL OUT2
Not Used
Not Used
Output Level
<3:2>
Power-Down
<1:0>
ON
Output Level
<3:2>
Power-Down
<1:0>
ON
LVDS_CMOS
OUT 3
Not Used
CMOS
Inverted
Logic
Output Level
Output
Power
LVDS, ON
Select
<2:1>
Driver On
41
LVDS_CMOS
OUT 4
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02
LVDS, ON
42, 43,
44
Not Used
CLK1 AND
CLK2
Input
Receivers
45
Clocks Select,
Power-Down
(PD) Options
Not Used
CLKs
in
PD
Not Used
Not
Used
CLK2
PD
CLK1
PD
Select
CLK IN
01
All Clocks
ON, Select
CLK1
46, 47,
48, 49
Not Used
DIVIDERS
Divider 0
Divider 0
4A
4B
Low Cycles <7:4>
High Cycles <3:0>
Phase Offset <3:0>
00
00
Divide by 2
Phase = 0
Bypass
Bypass
No
Force
Start H/L
Start H/L
Sync
4C
4D
Divider 1
Divider 1
Low Cycles <7:4>
High Cycles <3:0>
Phase Offset <3:0>
11
00
Divide by 4
Phase = 0
No
Force
Sync
4E
Divider 2
Low Cycles <7:4>
High Cycles <3:0>
33
Divide by 8
Rev. A | Page 37 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
