AD9512
Reg.
Addr.
(Hex)
Bit(s)
Name
Description
36
<5:1> Delay Fine Adjust
OUT4
Sets Delay Within Full Scale of the Ramp; There Are 32 Steps.
00000b => Zero Delay (Default).
11111b => Maximum Delay.
36
<7:6>
Not Used.
Not Used.
37 (38) <7:0>
(39)
(3A) (3B)
(3C)
OUTPUTS
3D (3E) <1:0> Power-Down LVPECL
(3F)
OUT0
(OUT1)
(OUT2)
Mode <1> <0>
Description
Output
ON
OFF
ON
0
0
1
0
1
0
Normal Operation.
Test Only—Do Not Use.
Safe Power-Down.
PD1
PD2
OFF
Partial Power-Down; Use If Output Has
Load Resistors.
PD3
1
1
Total Power-Down.
OFF
Use Only If Output Has No Load Resistors.
3D (3E) <3:2> Output Level LVPECL Output Single-Ended Voltage Levels for LVPECL Outputs.
(3F)
OUT0
(OUT1)
(OUT2)
<3>
<2>
Output Voltage (mV)
0
0
1
1
0
1
0
1
490
330
805 (Default)
650
3D (3E) <7:4>
(3F)
Not Used.
40 (41) <0>
Power-Down
LVDS/CMOS
OUT3
Power-Down Bit for Both Output and LVDS Driver.
0 = LVDS/CMOS on (Default).
1 = LVDS/CMOS Power-Down.
(OUT4)
40 (41) <2:1> Output Current Level
LVDS
OUT3
(OUT4)
<2>
0
<1>
0
Current (mA)
Termination (Ω)
1.75
100
100
50
0
1
3.5 (Default)
1
0
5.25
7
1
1
50
40 (41) <3>
40 (41) <4>
40 (41) <7:5>
LVDS/CMOS Select
OUT3
(OUT4)
0 = LVDS (Default).
1 = CMOS.
Inverted CMOS Driver Affects Output Only when in CMOS Mode.
OUT3
(OUT4)
0 = Disable Inverted CMOS Driver (Default).
1 = Enable Inverted CMOS Driver.
Not Used.
Rev. A | Page 40 of 48