AD9512
Reg.
Addr.
(Hex)
Bit(s)
<7>
Name
Description
Bypass Divider
OUT0
Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b).
4B
(4D)
(4F)
(51)
(53)
(OUT1)
(OUT2)
(OUT3)
(OUT4)
54 (55) <7:0>
(56) (57)
Not Used.
FUNCTION
58
58
<0>
<1>
SYNC Detect Enable
SYNC Select
1 = Enable SYNC Detect (Default = 0b).
1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.
0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles.
58
<2>
Soft SYNC
Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s
polarity is reversed. That is, a high level forces selected outputs into a known state, and a high >
low transition triggers a sync (Default = 0b).
58
58
58
<3>
<4>
Dist Ref Power-Down 1 = Power-Down the References for the Distribution Section (Default = 0b).
SYNC Power-Down 1 = Power-Down the SYNC (Default = 0b).
<6:5> FUNCTION Pin Select
<6>
<5>
0
Function
0
RESETB (Default)
SYNCB
0
1
1
0
Test Only; Do Not Use
PDB
1
1
58
59
5A
<7>
Not Used.
Not Used.
<7:0>
<0>
Update Registers
1 written to this bit updates all registers and transfers all serial control port register buffer
contents to the control registers on the next rising SCLK edge. This is a self-clearing bit. 0 does
not have to be written to clear it.
5A
<7:1>
Not Used.
END
Rev. A | Page 42 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
