AD9512
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9512 offers both LVPECL and
LVDS outputs, which are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second
differential output option for the AD9512. LVDS uses a current
mode output stage with several user-selectable current levels.
The normal value (default) for this current is 3.5 mA, which
yields 350 mV output swing across a 100 Ω resistor. The LVDS
outputs meet or exceed all ANSI/TIA/EIA—644 specifications.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9512 provide the lowest jitter clock signals
available from the AD9512. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. A simplified equivalent circuit in Figure 27 shows
the LVPECL output stage.
A recommended termination circuit for the LVDS outputs is
shown in Figure 44.
3.3V
3.3V
100Ω
100Ω
LVDS
LVDS
DIFFERENTIAL (COUPLED)
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 42. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the desired switching threshold (1.3 V).
Figure 44. LVDS Output Termination
3.3V
See Application Note AN-586 on the ADI website at
www.analog.com for more information on LVDS.
3.3V
3.3V
127Ω
127Ω
50Ω
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
SINGLE-ENDED
(NOT COUPLED)
LVPECL
LVPECL
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply bypassing and grounding to ensure optimum
performance.
50Ω
83Ω
83Ω
V
= V – 1.3V
CC
T
Figure 42. LVPECL Far-End Termination
3.3V
3.3V
0.1nF
DIFFERENTIAL
100Ω
LVPECL
LVPECL
(COUPLED)
0.1nF
200Ω
200Ω
Figure 43. LVPECL with Parallel Transmission Line
Rev. A | Page 45 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
