AD9512
APPLICATIONS
USING THE AD9512 OUTPUTS FOR ADC CLOCK
APPLICATIONS
level, termination) should be considered when selecting the best
clocking/converter solution.
Any high speed analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer; any noise,
distortion, or timing jitter on the clock is combined with the
desired signal at the A/D output. Clock integrity requirements
scale with the analog input frequency and resolution, with
higher analog input frequency applications at ≥14-bit resolution
being the most stringent. The theoretical SNR of an ADC is
limited by the ADC resolution and the jitter on the sampling
clock. Considering an ideal ADC of infinite resolution where
the step size and quantization error can be ignored, the available
SNR can be expressed approximately by
CMOS CLOCK DISTRIBUTION
The AD9512 provides two clock outputs (OUT3 and OUT4),
which are selectable as either CMOS or LVDS levels. When
selected as CMOS, these outputs provide for driving devices
requiring CMOS level logic at their clock inputs.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be followed.
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
⎡
⎢
⎤
⎥
1
2πft
SNR = 20×log
⎢
⎣
⎥
⎦
j
where f is the highest analog frequency being digitized, and tj is
the rms jitter on the sampling clock. Figure 39 shows the
required sampling clock jitter as a function of the analog
frequency and effective number of bits (ENOB).
t = 50fs
j
60.4Ω
1
2πft
SNR = 20log
120
10
1.0 INCH
j
10Ω
18
16
14
12
10
8
CMOS
t = 0.1ps
j
MICROSTRIP
100
80
t = 1ps
j
50pF
GND
t = 10ps
j
Figure 40. Series Termination of CMOS Output
60
40
20
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9512 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 41. The far-
end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing can still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
t = 100ps
j
6
t = 1ns
j
4
1
3
10
30
100
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
Figure 39. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 on the ADI website
at www.analog.com.
V
= 3.3V
PULLUP
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection, which can
provide superior clock performance in a noisy environment.)
The AD9512 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
100Ω
50Ω
10Ω
CMOS
3pF
OUT3, OUT4
100Ω
SELECTED AS CMOS
Figure 41. CMOS Output with Far-End Termination
requirements of the ADC (differential or single-ended, logic
Rev. A | Page 44 of 48
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