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AD9512 参数 Datasheet PDF下载

AD9512图片预览
型号: AD9512
PDF下载: 下载PDF文件 查看货源
内容描述: 1.2 GHz的时钟分配IC , 1.6 GHz的输入,分频器,延迟调整,五路输出 [1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs]
分类和应用: 时钟
文件页数/大小: 48 页 / 1007 K
品牌: ABCO [ ABCO ELECTRONICS CO.LTD ]
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AD9512  
REGISTER MAP DESCRIPTION  
Table 18 lists the AD9512 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle  
brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 18 describes the  
functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 17.  
Table 18. AD9512 Register Descriptions  
Reg.  
Addr.  
(Hex)  
Bit(s)  
Name  
Description  
Serial Control Port  
Configuration  
Any changes to this register takes effect immediately. Register 5Ah<0> Update Registers  
does not have to be written.  
00  
00  
<3:0>  
<4>  
Not Used.  
Long Instruction  
Soft Reset  
When this bit is set (1), the instruction phase is 16 bits. When clear (0), the instruction phase  
is 8 bits. The default, and only, mode for this part is long instruction (Default = 1b).  
00  
00  
00  
<5>  
<6>  
<7>  
When this bit is set (1), the chip executes a soft reset, restoring default values to the internal  
registers, except for this register, 00h. This bit is not self-clearing. A clear (0) has to be written  
to it in order to clear it.  
LSB First  
When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register  
addressing increments. If this bit is clear (0), data is oriented as MSB first and register  
addressing decrements. (Default = 0b, MSB first.)  
SDO Inactive  
(Bidirectional  
Mode)  
When set (1), the SDO pin is tri-state and all read data goes to the SDIO pin. When clear (0),  
the SDO is active (unidirectional mode). (Default = 0b).  
Not Used  
01 to 33 <7:0>  
Not Used.  
Fine Delay Adjust  
34  
<0>  
Delay Control  
OUT4  
Delay Block Control Bit.  
Bypasses Delay Block and Powers It Down (Default = 1b).  
34  
35  
<7:1>  
Not Used.  
<2:0> Ramp Current  
OUT4  
The slowest ramp (200 ꢀs) sets the longest full scale of approximately 10 ns.  
<2>  
0
<1>  
0
<0>  
0
Ramp Current (μs)  
200  
0
0
1
400  
0
1
0
600  
0
1
1
800  
1
1
1
1
0
0
1
1
0
1
0
1
1000  
1200  
1400  
1600  
35  
<5:3> Ramp Capacitor  
OUT4  
Selects the Number of Capacitors in Ramp Generation Circuit.  
More Capacitors => Slower Ramp.  
<5>  
0
<4>  
0
<3>  
0
Number of Capacitors  
4 (Default)  
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
3
3
2
3
2
2
1
35  
36  
<7:6>  
<0>  
Not Used.  
Not Used.  
Rev. A | Page 39 of 48