AD9512
POWER SUPPLY
The AD9512 requires a 3.3 V 5ꢀ power supply for VS.
The tables in the Specifications section give the performance
expected from the AD9512 with the power supply voltage
within this range. The absolute maximum range of −0.3 V to
+3.6 V, with respect to GND, must never be exceeded on
the VS pin.
POWER MANAGEMENT
The power usage of the AD9512 can be managed to use only the
power required for the functions that are being used. Unused
features and circuitry can be powered down to save power. The
following circuit blocks can be powered down, or are powered
down when not selected (see the Register Map and Description
section):
Good engineering practice should be followed in the layout of
power supply traces and ground plane of the PCB. The power
supply should be bypassed on the PCB with adequate
capacitance (>10 ꢁF). The AD9512 should be bypassed with
adequate capacitors (0.1 ꢁF) at all power pins, as close as
possible to the part. The layout of the AD9512 evaluation board
(AD9512/PCB) is a good example.
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Any of the dividers are powered down when bypassed—
equivalent to divide-by-one.
The adjustable delay block on OUT4 is powered down
when not selected.
Any output can be powered down. However, LVPECL
outputs have both a safe and an off condition. When the
LVPECL output is terminated, only the safe shutdown
should be used to protect the LVPECL output devices. This
still consumes some power.
The AD9512 is a complex part that is programmed for its
desired operating configuration by on-chip registers. These
registers are not maintained over a shutdown of external power.
This means that the registers can lose their programmed values
if VS is lost long enough for the internal voltages to collapse.
Careful bypassing should protect the part from memory loss
under normal conditions. Nonetheless, it is important that the
VS power supply not become intermittent, or the AD9512 risks
losing its programming.
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The entire distribution section can be powered down when
not needed.
Powering down a functional block does not cause the
programming information for that block (in the registers) to be
lost. This means that blocks can be powered on and off without
otherwise having to reprogram the AD9512. However,
synchronization is lost. A SYNC must be issued to
The internal bias currents of the AD9512 are set by the RSET
resistors. This resistor should be as close as possible to the value
given as conditions in the Specifications section
(RSET = 4.12 kΩ). This is a standard 1ꢀ resistor value and should
be readily obtainable. The bias currents set by this resistor
determine the logic levels and operating conditions of the
internal blocks of the AD9512. The performance figures given
in the Specifications section assume that this specific resistor
value is used.
resynchronize (see the Single-Chip Synchronization section).
The exposed metal paddle on the AD9512 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND). The PCB acts as a heat sink for the
AD9512; therefore, this GND connection should provide a
good thermal path to a larger dissipation area, such as a ground
plane on the PCB. See the layout of the AD9512 evaluation
board (AD9512/PCB or AD9512-VCO/PCB) for a good
example.
Rev. A | Page 43 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
