AD9512
tS
tH
CSB
tCLK
tHI
tLO
tDS
SCLK
SDIO
tDH
BI N
BI N + 1
Figure 37. Serial Control Port Timing—Write
Table 16. Serial Control Port Timing
Parameter
Description
tDS
tDH
tCLK
tS
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
tH
Hold time between CSB and SCLK
tHI
tLO
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
CSB TOGGLE INDICATES
CYCLE COMPLETE
tPWH
CSB
16 INSTRUCTION BITS + 8 DATA BITS
COMMUNICATION CYCLE 1
16 INSTRUCTION BITS + 8 DATA BITS
SCLK
SDIO
COMMUNICATION CYCLE 2
TIMING DIAGRAM FOR TWO SUCCESSIVE COMMUNICATION CYCLES. NOTE THAT CSB MUST
BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OFA COMMUNICATION CYCLE.
Figure 38. Use of CSB to Define Communication Cycles
Rev. A | Page 36 of 48
ABCO [ ABCO ELECTRONICS CO.LTD ]
