W89C840F
2
R/W
TBU
Transmit Buffer Unavailable
A high indicates that there is no available transmit descriptor
during or after the packet transmission. The transmit process will
stay in suspend state.
The TBU will not accumulate the number of transmit buffer
unavailable event, i.e. write an 1 value to TBU will clear the TBU,
no matter how many times the transmit buffer unavailable has been
occurred before the TBU is cleared.
1
0
R/W
R/W
TIDLE
TINI
Transmit Process in Idle State.
A high indicates the transmit state machine is in the idle state.
Transmit Interrupt
The TINI i s set when a frame transmit is completed and the FINT
(bit 31) of Transmit Descriptor 1 (T01) is set.
C18/CNCR Network Configuration Register
The register C18/CNCR defines the configuration for the data transmission or receiving and the interrupt
algorithm for interrupt assertion.
Bit
31
Attribute
R/W
Bit name
REIO
Description
Receive Early Interrupt On
The receive early interrupt function is enabled when the REIO is set
to high. Otherwise, the receive early interrupt function i s disabled.
During receiving packet data, the W89C840F will assert an
i nt er r upt r equest when t he byt e number of the received data,
which the receive DMA has moved them into the data buffer in the
system memory , excesses the receive early interrupt threshold.
30
R/W
TEIO
Transmit Early Interrupt On
The transmit early interrupt function i s enabled when the TEIO is
set to high. Otherwise, the transmit early interrupt function i s
disabled.
W89C840F asserts an early transmit interrupt when all the current
packet dat a have been moved i nt o t he t wo Kbytes transmit
FIFO no matter what data have been put onto the MII interface
completely or not.
29
R/W
FES
Fast Ethernet Select
When set, W89C840F will run in 100 Mbps mode. When reset,
W89C840F run in 10 Mbps mode. To change this bit, the transmit
state machine must be i n Idle state. The SQE test function i s
enabled when FES is reset to low.
Publication Release Date:April 1997
- 41 -
Revision A1
ETC [ ETC ]
