W89C840F
F08/FREV Device Revision Register
This register, a read-only with built-in code, shows W89C840F revision number and its class
code.
Bit
Attribute
R
Bit name
BC
Description
31:24
Base Class Code.
Fixed at 02h to indicate a network controller.
Subclass Code.
23:16
R
SC
Fixed at 00h to indicate a Ethernet controller.
Interface Code. Fixed at 0.
15:8
7:0
R
R
IC
REV
Revision ID.
This field represents the revision number.
Loaded from EEPROM after hardware reset de-asserted
F0C/FLT Latency Timer Register
This register specifies the W89C840F master bus latency timer.
Bit
Attribute
R
Bit name
---
Description
Fixed to 0.
31:16
15:8
R/W
LT
Latency Timer.
Specify, in units of PCI clocks, the latency timer value of
W89C840F. When W89C840F asserts FRAMEB, its latency timer
starts counting up. The W89C840F will initiate the transaction
termination when its GNT# de-asserted If the timer expired before
W89C840F de-asserts FRAMEB.
7:0
R
---
Fixed at 0.
Publication Release Date:April 1997
- 29 -
Revision A1
ETC [ ETC ]
