W89C840F
24
R/W
DPED
Data Parity Error Detected.
The DPED will be set if the following three conditions are met:
1). The W89C840F asserts PERRB or detects out that PERRB
asserted by other device.
2). The W89C840F acts as a master in the transaction that the
error occurs.
3). The parity error response bit (bit 6) is set.
Fast Back to Back Capable.
23
R
FBTBC
Fixed at 1 to indicate capability of accepting fast back to back
transactions that are not accessing to the same target.
22:9
8
R
---
Reserved. Fixed at 0.
SERR# Enable.
R/W
SE
Set SE high to enable the W89C840F to assert SERR# if an
address parity error is detected. This bit and bit 6 must be set 1 to
signal SERR event.
7
6
R
----
Reserved. Fixed at 0.
Parity Error Response.
R/W
PER
Set PER to high to enable the W89C840F to respond to parity
error.
When PER is reset, the W89C840F will ignore any parity error
and continue the normal operation.
The W89C840F internal parity checking and generation function
will not be disabled even PER is reset.
5:3
2
R
---
Reserved. Fixed at 0.
R/W
BM
Bus Master.
Set BM to high will allow W89C840F acting as a bus master.
Reset BM to low will disable the W89C840F‘ s bus master ability.
Memory Space.
1
0
R/W
R/W
MS
Set MS to high will allow W89C840F to respond to memory space
access by the host.
IOS
I/O Space.
Set IOS to high will allow W89C840F to respond to I/O space
access by the host.
- 28 -
ETC [ ETC ]
