W89C840F
F00/FID Device ID Register
The register F00/FID specifies the vendor ID and the particular device ID in the W89C840F.
Bit
31:16
15:0
Attribute Bit name
Description
R
DID
VID
Device ID. Loaded from EEPROM after hardware reset de-asserted.
VendorID. Loaded from EEPROM after hardware reset de-asserted.
R
F04/FCS Command and Status Register
The F04/ FCS compr i ses t wo par t s, one is the command register (FCS[15:0]) which provides
the control of 840 PCI activity, and the other is the status register (FCS[31:16]) which shows the status
information of PCI event.
Writing 00h to the command registers will put W89C840F logically isolated from all PCI access
except configuration access.
Writing 1 to the bits of the status register will clear them; writing 0 has no effect.
Bit
31
Attribute
R/W
Bit name
DPE
Description
Detected Parity Error.
The DPE will be set if a parity error is detected by W89C840F
even the parity error response bit of F04/FCS(bit 6) is disabled.
30
29
R/W
R/W
SSE
Signaled System Error.
The SSE will be set if W89C840F assert SERRB.
Received Master Abort.
RMA
The RMA will be set if W89C840F master transaction takes a
master abort.
28
R/W
R/W
R
RTA
STA
DT
Received Target Abort.
The RTA will be set if the 840 master transaction is terminated by
a target abort.
27
Signaled Target Abort.
The STA will be set if the W89C840F slave transactions take a
target abort.
26:25
DEVSEL# Timing:
Fixed at 01 to indicate a medium DEVSEL# assert timing.
Publication Release Date:April 1997
- 27 -
Revision A1
ETC [ ETC ]
