W89C840F
System resource configuring function
The W89C840F will require the I/O space, memory space and the interrupt line to perform the
communication between the network and the host.
The system BIOS can write all 1 data into the register F10/FBIOA and read back its value to
determine how large the I/O space the W89C840F requires. The W89C840F will return a FFFFF801H
value if the system BIOS has previously written all 1 value into the F10/FBIOA. This means that the
W89C840F requires 128 bytes system I/O space. The I/O space allocated for the W89C840F is relied on
which I/O address base is written into F10/FBIOA. The W89C840F will decode the address message
based on the content of the register F10/FBIOA to determine if the current PCI transaction is accessed to
its registers.
For memory space allocation, the system BIOS can write all 1 value into the register F14/FBMA
of the W89C840F and read back its value to determine how large memory space the W89C840F
requires. The W89C840F will also return FFFFF801H value if the system BIOS has previously written
all 1 value into the register F14/FBMA. This means that the W89C840F requires 128 bytes system
memory space. The memory space allocated for the W89C840F depends on which memory address base
is written into the register F14/FBMA. The W89C840F will decode the address message based on the
content of the register F14/FBMA to determine if the current PCI transaction is accessed to its registers.
The W89C840F uses only one interrupt pin, INTA#. However, the interrupt line resource
assignment is determined by the system BIOS by writing the related data into the bits 0 to 7 of the
register F3C/FIR in the W89C840F. The data written into the bits0 to 7 of the register F3C/FIR can be
used by the driver program to decide the interrupt service subroutine configuring.
PCI Configuration register
The general attributes of the PCI configuration registers implemented in the W89C840F are described
as the following:
1) Wr i t e to the reserved configuration registers are treated as no-op. The bus access will complete
without affecting any data in the W89C840F internal registers.
2) Read from the reserved or un-implemented registers will be returned 0‘ s value.
3) S/W reset has no effect on the PCI configuration registers.
4) H/W reset will clear the PCI configuration registers.
5) The implemented configuration registers support any byte enable combination access.
6) Burst access to the configuration registers will be terminated after 1st data transfer completed with
a with a disconnect without data.
Publication Release Date:April 1997
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Revision A1
ETC [ ETC ]
