W89C840F
Usually, the on-board boot ROM data can be read by the system BIOS during host syst em
boot i ng or power - up/ r eset . W89C840F also provides another access way for the application
program to do some unusual appl i cat i ons, such as down loading the ROM code or re-
programming the ROM code on line.
The procedures for on-line reading the on-board ROM device are described as following.
1) Write the offset address into the C28/CBROA.
2) Reset the bit 11 of C24/CMIIR to 0.
3) Set the bit 14 of C24/CMIIR to 1.
4) read back the data form C24/CMIIR
The procedures for on-line writing the on-board ROM device are described as following
1) Write the offset address into the C28/CBROA.
2) Reset the bit 11 of C24/CMIIR to 0.
3) Write the one byte data into C24/CMIIR bit 0 to bit 7.
4) Set the bit 13 of C24/CMIIR to 1.
The bit 13 and bit 14 of the register C24/CMIIR should not be set to 1 at the same time. In the
case of both of the bit 13 and bit 14 are 1, it will not properly initialize the read or the write operation for
ROM device. The application program can check the contents of the register C24/CMIIR to know if the
read or write operation is already completed or not. The W89C840F will start the read or the write
operation when the bit 14 or bit 13 are set to high and will reset the bit 14 or bit 13 to 0 automatically
after the read/write operation is completed. For the writing operation, the software driver should not start
up the next write data request until the bit 13 of C24/CMIIR is reset to 0 by the W89C840F. For the read
operation, the read data will be valid only if the bit 14 of the register C24/CMIIR is reset to 0 by the
W89C840F.
The operation of reading or writing for the on-board ROM device through the registers
C24/CMIIR and C28/CBROA will not affect the memory space configuration of the host system because
either read or write operation is performed through the PCI I/O access command.
MII management function
The MII management function provided by W89C840F can be used to access the registers of the
external physical layer device. The bits 16, 17, 18 and 19 of C24/CMIIR are designed for MII
management. When t he bi t 18 i s r eset low, the MDIO signal on MII bus is an input of W89C840F.
The data on the MDIO will be reflected transparently on the bit 19 of the register C24/CMIIR. While the
bit 18 is set to high, the MDIO signal on MII will be changed to be an output pin of W89C840F and the
data written to the bit 17 of the register C24/CMIIR will be driven onto the MDIO. To generate the
necessary clock for MII management, the application program can write 1 and 0 alternately to the bit 16
of the register C24/CMIIR. The clock is used by the external physical layer device to clock in the written
data or to clock out the read data.
- 24 -
ETC [ ETC ]
