VT82C686B
Offset 83-80 – Primary S/G Descriptor Address ............RW
Offset 8B-88 – Secondary S/G Descriptor Address........RW
IDE I/O Registers
These registers are compliant with the SFF 8038I v1.0
standard. Refer to the SFF 8038I v1.0 specification for further
details.
I/O Offset 0 - Primary Channel Command
I/O Offset 2 - Primary Channel Status
Offset C3-C0 – PCI PM Block 1 .......................................RO
................. always reads 0002 0001h
31-0 PCI PM Block 1
Offset C7-C4 – PCI PM Block 2 .......................................RO
I/O Offset 4-7 - Primary Channel PRD Table Address
........................................ always reads 0
.....................................................default
31-2 Reserved
1-0 Power State
00 On
01 Off
1x -reserved-
I/O Offset 8 - Secondary Channel Command
I/O Offset A - Secondary Channel Status
I/O Offset C-F - Secondary Channel PRD Table Address
Revision 1.71 June 9, 2000
-74-
Function 1 Registers - Enhanced IDE Controller
ETC [ ETC ]
