VT82C686B
Function 3 Registers - USB Controller Ports 2-3
Offset 8 - Revision ID (nnh).............................................. RO
7-0 Silicon Revision Code (0 indicates first silicon)
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 3 PCI configuration space of the
VT82C686B. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 2-3 (see function 2 for ports 0-1).
Offset 9 - Programming Interface (00h) .......................... RO
Offset A - Sub Class Code (03h=USB Controller) .......... RO
Offset B - Base Class Code (0Ch=Serial Bus Controller)RO
Offset C – Cache Line Size (00h)...................................... RO
Offset D - Latency Timer ................................................. RW
PCI Configuration Space Header
..........................................default = 16h
7-0 Timer Value
Offset 1-0 - Vendor ID .......................................................RO
Offset E - Header Type (00h)............................................ RO
Offset F - BIST (00h)......................................................... RO
Offset 23-20 - USB I/O Register Base Address............... RW
................. (1106h = VIA Technologies)
0-7 Vendor ID
Offset 3-2 - Device ID.........................................................RO
(3038h = VT82C686B USB Controller)
Offset 5-4 - Command.......................................................RW
........................................ always reads 0
0-7 Device ID
........................................always reads 0
31-16 Reserved
Port Address for
15-5 USB I/O Register Base Address.
15-8 Reserved
the base of the 32-byte USB I/O Register block,
corresponding to AD[15:5]
4-0 00001b
...................... default=0 (disabled)
(parity error response) ..................fixed at 0
(VGA palette snoop) ....................fixed at 0
7
6
5
4
3
2
1
0
Address Stepping
Reserved
Reserved
. default=0 (disabled)
Memory Write and Invalidate
Offset 3C - Interrupt Line (00h)...................................... RW
(special cycle monitoring) ............fixed at 0
Reserved
........................................always reads 0
7-4 Reserved
............................... default=0 (disabled)
Bus Master
Memory Space
........................default = 16h
3-0 USB Interrupt Routing
........................... default=0 (disabled)
0000 Disable................................................... default
............................... default=0 (disabled)
I/O Space
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disable
Offset 7-6 - Status...........................................................RWC
(detected parity error).......... always reads 0
15 Reserved
.............................. default=0
.............................. default=0
.............................. default=0
.............................. default=0
14 Signalled System Error
13 Received Master Abort
12 Received Target Abort
11 Signalled Target Abort
10-9 DEVSEL# Timing
00 Fast
01 Medium......................................default (fixed)
10 Slow
11 Reserved
........................................ always reads 0
8-0 Reserved
Offset 3D - Interrupt Pin (04h)......................................... RO
Revision 1.71 June 9, 2000
-78-
Function 3 Registers - USB Controller Ports 2-3
ETC [ ETC ]
