VT82C686B
Offset 54 – UltraDMA FIFO Control (06h)....................RW
........................................ always reads 0
Offset 61-60 - Primary Sector Size (0200h) .................... RW
........................................always reads 0
7-5 Reserved
15-12 Reserved
...def=200h (512 bytes)
4
One Frame For Each PCI Request For IDE PCI
Master Cycles
11-0 Number of Bytes Per Sector
Offset 69-68 - Secondary Sector Size (0200h)................. RW
0
Disable ...................................................default
........................................always reads 0
15-12 Reserved
1
Enable
...def=200h (512 bytes)
11-0 Number of Bytes Per Sector
........................................ always reads 0
Change Drive to Clear All FIFO & Internal States
3
2
Reserved
0
Disable
1
Enable.....................................................default
........................................ always reads 0
Complete DMA Cycle with Transfer Size Less
Than FIFO Size
1
0
Reserved
0
Enable.....................................................default
1
Disable
Revision 1.71 June 9, 2000
-72-
Function 1 Registers - Enhanced IDE Controller
ETC [ ETC ]
