VT82C686B
Offset 70 – Primary IDE Status .......................................RW
Offset 78 – Secondary IDE Status ................................... RW
7
6
5
4
3
2
1
0
Interrupt Status
7
6
5
4
3
2
1
0
Interrupt Status
Prefetch Buffer Status
Post Write Buffer Status
DMA Read Prefetch Status
DMA Write Prefetch Status
S/G Operation Complete
FIFO Empty Status
Prefetch Buffer Status
Post Write Buffer Status
DMA Read Prefetch Status
DMA Write Prefetch Status
S/G Operation Complete
FIFO Empty Status
Response to External DMAREQ
Response to External DMAREQ
Offset 71 – Primary Interrupt Control............................RW
........................................ always reads 0
Flush FIFO Before Generating IDE Interrupt
Offset 79 - Secondary Interrupt Control........................ RW
........................................always reads 0
Flush FIFO Before Generating IDE Interrupt
7-1 Reserved
0
7-1 Reserved
0
0
Disable ...................................................default
0
Disable................................................... default
1
Enable
1
Enable
Revision 1.71 June 9, 2000
-73-
Function 1 Registers - Enhanced IDE Controller
ETC [ ETC ]
