VT82C686B
Offset 42 - FIFO Control..................................................RW
USB I/O Registers
........................................ always reads 0
7-4 Reserved
These registers are compliant with the UHCI v1.1 standard.
Refer to the UHCI v1.1 specification for further details.
.................... default = 0
3-2 Reserved (Do Not Program)
1-0 Release Continuous REQ After “N” PCICLKs
00 Do Not Release ......................................default
01 N = 32 PCICLKs
I/O Offset 1-0 - USB Command
10 N = 64 PCICLKs
11 N = 96 PCICLKs
I/O Offset 3-2 - USB Status
I/O Offset 5-4 - USB Interrupt Enable
I/O Offset 7-6 - Frame Number
Offset 60 - Serial Bus Release Number.............................RO
.............................. always reads 10h
7-0 Release Number
I/O Offset B-8 - Frame List Base Address
I/O Offset 0C - Start Of Frame Modify
I/O Offset 11-10 - Port 0 Status / Control
I/O Offset 13-12 - Port 1 Status / Control
Offset 83-80 – PM Capability............................................RO
.................... always reads 00020001h
31-0 PM Capability
Offset 84 – PM Capability Status ....................................RW
........................... default = 00h
7-0 PM Capability Status
Supports 00h (Off) and 11h (On) only
Offset C1-C0 - Legacy Support.........................................RO
................ always reads 2000h
15-0 UHCI v1.1 Compliant
Revision 1.71 June 9, 2000
-77-
Function 2 Registers - USB Controller Ports 0-1
ETC [ ETC ]
