VT82C686B
Offset 4B-48 - Drive Timing Control (A8A8A8A8h)......RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals:
Offset 53-50 - UltraDMA Extended Timing Control..... RW
31 Pri Drive 0 UltraDMA-Mode Enable Method
0
Enable by using “Set Feature” command.....def
1
Enable by setting bit-30 of this register
...... def=1010b
............. def=1000b
...... def=1010b
............. def=1000b
31-28 Primary Drive 0 Active Pulse Width
27-24 Primary Drive 0 Recovery Time
23-20 Primary Drive 1 Active Pulse Width
19-16 Primary Drive 1 Recovery Time
30 Pri Drive 0 UltraDMA-Mode Enable
0
1
Disable................................................... default
Enable UltraDMA-Mode Operation
29 Pri Drive 0 Transfer Mode
.. def=1010b
15-12 Secondary Drive 0 Active Pulse Width
0
1
DMA or PIO Mode ............................... default
UltraDMA Mode
......... def=1000b
11-8 Secondary Drive 0 Recovery Time
.. def=1010b
......... def=1000b
7-4 Secondary Drive 1 Active Pulse Width
28 Pri Drive 0 Cabal Type Reporting
3-0 Secondary Drive 1 Recovery Time
0
1
Disable................................................... default
Enable
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks.
........................................always reads 0
27 Reserved
26-24 Pri Drive 0 Cycle Time (T = 10nsec)
Offset 4C - Address Setup Time (FFh)............................RW
000 2T
001 3T
010 4T
011 5T
100 6T
101 7T
110 8T
........ def = 11
....... def = 11
7-6 Primary Drive 0 Address Setup Time
5-4 Primary Drive 1 Address Setup Time
3-2 Secondary Drive 0 Address Setup Time
1-0 Secondary Drive 1 Address Setup Time
.... def = 11
.... def = 11
For each field above:
00 1T
01 2T
111 9T
.................................................... default
10 3T
11 4T
23 Pri Drive 1 UltraDMA-Mode Enable Method
22 Pri Drive 1 UltraDMA-Mode Enable
21 Pri Drive 1 Transfer Mode
.....................................................default
20 Pri Drive 1 Cabal Type Reporting
0
Disable................................................... default
1
Enable
........................................always reads 0
19 Reserved
.......... (see above for default)
18-16 Pri Drive 1 Cycle Time
15 Sec Drive 0 UltraDMA-Mode Enable Method
14 Sec Drive 0 UltraDMA-Mode Enable
13 Sec Drive 0 Transfer Mode
12 Sec Drive 0 Cabal Type Reporting
0
Disable................................................... default
1
Enable
........................................always reads 0
11 Reserved
......... (see above for default)
10-8 Sec Drive 0 Cycle Time
7
6
5
4
Sec Drive 1 UltraDMA-Mode Enable Method
Sec Drive 1 UltraDMA-Mode Enable
Sec Drive 1 Transfer Mode
Sec Drive 1 Cabal Type Reporting
0
Disable................................................... default
1
Enable
........................................always reads 0
......... (see above for default)
3
Reserved
2-0 Sec Drive 1 Cycle Time
Each byte defines UltraDMA operation for the indicated drive.
The bit definitions are the same within each byte.
Revision 1.71 June 9, 2000
-71-
Function 1 Registers - Enhanced IDE Controller
ETC [ ETC ]
