VT82C686B
IDE-Controller-Specific Confiiguration Registers
Offset 40 - Chip Enable (00h)...........................................RW
Offset 44 - Miscellaneous Control 1 (68h) ...................... RW
........................................ always reads 0
........................................always reads 0
Reserved
Master Read Cycle IRDY# Wait States
7-4 Reserved
7
6
...........R/W, default = 0
3-2 Reserved (Do Not Program)
0
1
0 wait states
1 wait state............................................. default
........ default = 0 (disabled)
1
0
Primary Channel Enable
.... default = 0 (disabled)
Secondary Channel Enable
5
4
3
Master Write Cycle IRDY# Wait States
Offset 41 - IDE Configuration I (06h) .............................RW
0
0 wait states
7
6
5
4
Primary IDE Read Prefetch Buffer
1
1 wait state............................................. default
0
Disable ...................................................default
PIO Read Prefetch Byte Counter
1
Enable
0
Disable................................................... default
Primary IDE Post Write Buffer
1
Enable
0
Disable ...................................................default
Bus Master IDE Status Register Read Retry
Retry bus master IDE status register read when
master write operation for DMA read is not complete
1
Enable
Secondary IDE Read Prefetch Buffer
0
Disable ...................................................default
0
1
Disable
1
Enable
Enable.................................................... default
Secondary IDE Post Write Buffer
2
Packet Command Prefetching
0
Disable ...................................................default
0
Disable................................................... default
1
Enable
1
Enable
........................................ always reads 0
...................... default=1
Reserved (Do Not Program)
3-2 Reserved
........................................always reads 0
UltraDMA Host Must Wait for First Strobe
Before Termination
1
0
Reserved
1
0
........................................ always reads 0
Reserved
0
1
Enable.................................................... default
Disable
Offset 42 - IDE Configuration II (09h)............................RW
........ default = 000010b
7-2 Reserved (Do Not Program)
Offset 45 - Miscellaneous Control 2 (00h) ...................... RW
..................... default = 01b
1-0 DEVSEL# Timing Select
(also reflected in Rx07)
........................................always reads 0
Interrupt Steering Swap
7
6
Reserved
Offset 43 - FIFO Configuration (0Ah).............................RW
........................................ always reads 0
0
Don’t swap channel interrupts ............... default
7-4 Reserved
1
Swap interrupts between the two channels
3-2 Threshold for Primary Channel
........................................always reads 0
5
4
Reserved
00 0
01 1/4
Rx3C Write Protect
0
Disable................................................... default
10 1/2
.....................................................default
1
Enable
11 3/4
3
2
Memory Read Multiple Command
1-0 Threshold for Secondary Channel
0
Disable................................................... default
00 0
01 1/4
1
Enable
Memory Read and Invalidate Command
10 1/2
11 3/4
.....................................................default
0
Disable................................................... default
1
Enable
........................................always reads 0
Offset 46 - Miscellaneous Control 3 (C0h) ..................... RW
1-0 Reserved
7
Primary Channel Read DMA FIFO Flush
0
Disable
1
Enable FIFO flush for Read DMA when
interrupt asserts primary channel. .......... default
6
Secondary Channel Read DMA FIFO Flush
0
Disable
1
Enable FIFO flush for Read DMA when
interrupt asserts secondary channel........ default
........................................always reads 0
5-0 Reserved
Revision 1.71 June 9, 2000
-70-
Function 1 Registers - Enhanced IDE Controller
ETC [ ETC ]
