VT82C686B
Function 1 Registers - Enhanced IDE Controller
Offset 9 - Programming Interface ................................... RW
........... fixed at 1 (Supported)
Master IDE Capability
7
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT82C686B. The Bus Master IDE I/O registers are defined in
the SFF8038i v1.0 specification.
........................................always reads 0
6-4 Reserved
...... fixed at 1
Supports both modes (may be set to either mode by
writing bit-2)
3
Programmable Indicator - Secondary
........................................always reads 0
2
1
Reserved
.......... fixed at 1
Programmable Indicator - Primary
Supports both modes (may be set to either mode by
writing bit-0)
PCI Configuration Space Header
........................................always reads 0
0
Reserved
Offset 1-0 - Vendor ID (1106h=VIA)................................RO
Offset 3-2 - Device ID (0571h=IDE Controller)...............RO
Offset 5-4 - Command.......................................................RW
Compatibility Mode (fixed IRQs and I/O addresses):
Command Block
Registers
Control Block
Registers
3F6
Channel
Pri
IRQ
14
15
1F0-1F7
Sec
170-177
376
........................................ always reads 0
15-10 Reserved
....... default = 0 (disabled)
Fast Back to Back Cycles
9
8
7
Native PCI Mode (registers are programmable in I/O space)
......................... default = 0 (disabled)
SERR# Enable
Command Block
Registers
BA @offset 10h
Control Block
Registers
BA @offset 14h
......................
Address Stepping
fixed at 1 (enabled)
Channel
Pri
A value of 1 provides additional address decode time
to IDE devices.
............ default = 0 (disabled)
Parity Error Response
Sec
BA @offset 18h BA @offset 1Ch
6
5
4
3
2
Command register blocks are 8 bytes of I/O space
Control registers are 4 bytes of I/O space (only byte 2 is used)
....................fixed at 0 (disabled)
VGA Palette Snoop
.....fixed at 0 (disabled)
Memory Write & Invalidate
.............................fixed at 0 (disabled)
Special Cycles
Offset A - Sub Class Code (01h=IDE Controller)........... RO
Offset B - Base Class Code (01h=Mass Storage Ctrlr)... RO
Offset C – Cache Line Size (00h)...................................... RO
Offset D - Latency Timer (Default=0)............................. RW
Offset E - Header Type (00h)............................................ RO
Offset F - BIST (00h)......................................................... RO
............................. default = 0 (disabled)
Bus Master
S/G operation can be issued only when the “Bus
Master” bit is enabled.
............................fixed at 0 (disabled)
1
0
Memory Space
............................. default = 0 (disabled)
I/O Space
When the “I/O Space” bit is disabled, the device will
not respond to any I/O addresses for both compatible
and native mode.
Offset 7-6 - Status...............................................................RO
........................ always reads 0
...................... always reads 0
...................... always reads 0
...................... always reads 0
...................... always reads 0
15 Detected Parity Error
14 Signalled System Error
13 Received Master Abort
12 Received Target Abort
11 Signalled Target Abort
............always reads 01 (medium)
10-9 DEVSEL# Timing
.......................... always reads 0
Data Parity Detected
.............................. always reads 1
Fast Back to Back
8
7
........................................ always reads 0
6-0 Reserved
Offset 8 - Revision ID (06) .................................................RO
0-7 Revision Code for IDE Controller Logic Block
Revision 1.71 June 9, 2000
-68-
Function 1 Registers - Enhanced IDE Controller
ETC [ ETC ]
