VT82C686B
Offset 88 – PLL Test .........................................................RW
Offset 8A – PCS2/3 I/O Port Address Mask................... RW
7
6
PCS0# Access Status
RTC Rx32 / Rx7F Write Protect
7-4 PCS3# I/O Port Address Mask 3-0
3-0 PCS2# I/O Port Address Mask 3-0
0
1
Disable ...................................................default
Enable
Offset 8B – PCS Control .................................................. RW
7
6
5
4
3
2
1
0
PCS3# For Internal I/O
5
4
3
MC IRQ Test (Do Not Program)
0
Disable................................................... default
0
1
Disable ...................................................default
Enable
1
Enable
PCS2# For Internal I/O
PLL PU (Do Not Program)
0
Disable................................................... default
0
1
Disable ...................................................default
Enable
1
Enable
PCS1# For Internal I/O
PLL Test Mode (Do Not Program)
0
Disable................................................... default
0
1
Disable ...................................................default
Enable
1
Enable
PCS0# For Internal I/O
2-0 PLL Test Mode Select
0
Disable................................................... default
1
Enable
PCS3#
Offset 89 – PLL Control ...................................................RW
0
Disable................................................... default
........................................ always reads 0
7-4 Reserved
3-2 PLL PCLK Input Delay Select
1-0 PLL CLK66 Feedback Delay Select
1
Enable
PCS2#
0
Disable................................................... default
1
Enable
PCS1#
0
Disable................................................... default
1
Enable
PCS0#
0
Disable................................................... default
1
Enable
Offset 8D-8C – PCS2# I/O Port Address........................ RW
15-0 PCS2# I/O Port Address
Offset 8F-8E – PCS3# I/O Port Address......................... RW
15-0 PCS3# I/O Port Address
Revision 1.71 June 9, 2000
-67-
Function 0 Registers - PCI to ISA Bridge
ETC [ ETC ]
