VT82C686B
Offset 40 –Hardware Monitor Configuration ................RW
7
Initialization
0
Normal operation ...................................default
1
Restore power-up default values to this
register, the interrupt status and mask registers,
the FAN/RST#/OS# register, and the OS#
Configuration
/
Temperature Resolution
register. This bit automatically clears itself
since the power-on default is 0.
6
Chassis Intrusion Reset
0
1
Normal operation ...................................default
Reset the Chassis Intrusion pin
........................................ default = 0
5-4 Reserved (R/W)
3
Hardware Monitor Interrupt Clear
0
Normal operation
1
Clear the hardware monitor interrupt output
(does not effect the contents of the interrupt
status register). Normally set during interrupt
service ....................................................default
........................................ always reads 0
Hardware Monitor Interrupt Enable
2
1
Reserved
0
Disable hardware monitor interrupt output.. def
1
Start
0
Enable hardware monitor interrupt output
0
Place hardware monitor in standby mode.... def
Enable startup of hardware monitor logic.
At startup, limit checking functions and
scanning begins. All high and low limits
should be set prior to turning on this bit. Note:
the hardware monitor interrupt output will not
be cleared if the user writes a zero to this bit
after an interrupt has occurred (the hardware
monitor interrupt clear bit must be used for this
purpose).
1
Revision 1.71 June 9, 2000
-103-
Hardware Monitor I/O Space Registers
ETC [ ETC ]
