VT82C686B
Offset 41 –Hardware Monitor Interrupt Status 1...........RO
Offset 43 –Hardware Monitor Interrupt Mask 1 .......... RW
7
6
5
4
Fan 2 Error
7
6
5
Fan 2 Count Error Mask
0
No error..................................................default
0
Enable interrupt on error status bit set.........def
1
Fan 2 count limit exceeded
1
Disable interrupt on error status bit set
Fan 1 Error
Fan 1 Count Error Mask
0
1
No error..................................................default
Fan 1 count limit exceeded
........................................ always reads 0
0
Enable interrupt on error status bit set.........def
1
Disable interrupt on error status bit set
Reserved
TSENS1 Thermal Alarm Control Mask
0
Enable TSENS1 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set )def
Disable
TSENS1 Temperature Error
0
1
No error..................................................default
High or low hot temperature limit exceeded.
The interrupt mode is determined by
Temperature Resolution register Rx4B[1-0].
1
4
3
2
1
0
TSENS1 Temperature Error Mask
0
Enable interrupt on error status bit set.........def
1
Disable interrupt on error status bit set
VSENS3 Voltage Error Mask (5V)
3
2
1
0
VSENS3 Voltage Error (5V)
0
Enable interrupt on error status bit set.........def
0
No error..................................................default
1
Disable interrupt on error status bit set
1
High or low limit exceeded
Internal Core VCC Voltage Error Mask (3.3V)
Internal Core VCC Voltage Error (3.3V)
0
Enable interrupt on error status bit set.........def
0
No error..................................................default
1
Disable interrupt on error status bit set
1
High or low limit exceeded
VSENS2 Voltage Error Mask (2.5V NB Core)
VSENS2 Voltage Error (2.5V NB Core Voltage)
0
Enable interrupt on error status bit set.........def
0
No error..................................................default
1
Disable interrupt on error status bit set
1
High or low limit exceeded
VSENS1 Voltage Error Mask (2.0V CPU Core)
VSENS1 Voltage Error (2.0V CPU Core Voltage)
0
Enable interrupt on error status bit set.........def
0
No error..................................................default
1
Disable interrupt on error status bit set
1
High or low limit exceeded
Offset 44 –Hardware Monitor Interrupt Mask 2 .......... RW
Offset 42 –Hardware Monitor Interrupt Status 2...........RO
TSENS3 (Internal Bandgap) Temp Error
7
TSENS3 Temperature Error Mask
7
0
1
Enable interrupt on error status bit set.........def
Disable interrupt on error status bit set
0
1
No error..................................................default
High or low hot temperature limit exceeded.
Interrupt mode is determined by Rx4B[5-4].
6
TSENS3 Thermal Alarm Control Mask
0
Enable TSENS3 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set) def
Disable
........................................ always reads 0
Chassis Error
6-5 Reserved
4
0
1
No error..................................................default
Chassis Intrusion has gone high
1
5
TSENS2 Thermal Alarm Control Mask
3
TSENS2 Temperature Error
0
Enable TSENS2 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set)def
Disable
0
1
No error..................................................default
High or low hot temperature limit exceeded.
Interrupt mode is determined by Rx4B[3-2].
1
........................................ always reads 0
2-1 Reserved
4
3
Chassis Error Mask
0
VSENS4 Voltage Error (12V)
0
Enable interrupt on error status bit set.........def
0
No error..................................................default
1
Disable interrupt on error status bit set
1
High or low limit exceeded
TSENS2 Temperature Error Mask
Note: When either status register is read, status conditions in
that register are reset. In the case of voltage priority
indications, if two or more voltages were out of limits, then
another indication would automatically be generated if it was
not handled during interrupt service. Errant voltages may be
disabled in the control register until the operator has time to
clear the errant condition or set the limit higher or lower.
0
Enable interrupt on error status bit set.........def
1
Disable interrupt on error status bit set
........................................always reads 0
VSENS4 Voltage Error Mask (12V)
2-1 Reserved
0
0
Enable interrupt on error status bit set.........def
1
Disable interrupt on error status bit set
Revision 1.71 June 9, 2000
-104-
Hardware Monitor I/O Space Registers
ETC [ ETC ]
