VT82C686B
Offset 47 –Hardware Monitor Fan Configuration.........RW
Offset 4B –Temperature Interrupt Configuration ........ RW
..................def = 00
7-6 TSENS1 Value Low-Order Bits
7-6 Fan 2 RPM Control
00 Divide by 1
Upper 8 bits are stored in offset 20h
5-4 TSENS3 Hot Temp Interrupt Mode
3-2 TSENS2 Hot Temp Interrupt Mode
1-0 TSENS1 Hot Temp Interrupt Mode
01 Divide by 2 ............................................default
10 Divide by 4
11 Divide by 8
...........def = 01
...........def = 01
...........def = 01
5-4 Fan 1 RPM Control
00 Divide by 1
The following applies to each of the above 3 fields
00 Default Interrupt Mode. An interrupt occurs if
the temperature goes above the hot limit. The
interrupt will be cleared once the status register
is read, but will be generated again when the
next conversion is completed. Interrupts will
continue to be generated until the temperature
goes below the hysteresis limit.
01 Divide by 2 ............................................default
10 Divide by 4
11 Divide by 8
........................................ always reads 0
3-0 Reserved
Offset 49 –Hardware Monitor Temp Low Order ValueRW
7-6 TSENS3 Value Low-Order Bits
Upper 8 bits are stored in offset 1Fh
5-4 TSENS2 Value Low-Order Bits
Upper 8 bits are stored in offset 21h
01 One-Time Interrupt Mode. An interrupt is
generated if the temperrature goes above the
hot limit. The interrupt will be cleared when
the status register is read. Another interrupt
will not be generated until the temperature first
drops below the hysteresis limit............. default
10 Comparator mode. An interrupt occurs if the
temperature goes above the hot limit. This
interrupt remains active until the temperature
goes below the hot limit (i.e., no hysteresis).
11 Default Interrupt Mode (same as 00)
3
Over Temperature Active Low for PMU to
Control Stop Clock
0
Disable ...................................................default
1
Enable
2
1
0
Chassis Active Low Output 20 msec
0
Disable ...................................................default
1
Enable
Interrupt Active High Output
0
Disable ...................................................default
1
Enable
........................................ always reads 0
Reserved
Revision 1.71 June 9, 2000
-105-
Hardware Monitor I/O Space Registers
ETC [ ETC ]
