VT82C686B
(00h)
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
Offset 9 - Programming Interface
........................... RO
The codec interface is hardware compatible with AC97 and
SoundBlaster Pro. There are two sets of software accessible
registers: PCI configuration registers and I/O registers. The
(01h=Audio Device)
Offset A - Sub Class Code
............... RO
(04h=Multimedia Device)
Offset B - Base Class Code
..... RO
PCI configuration registers for the
are located in
Audio Codec
(00h)
Offset D - Latency Timer
......................................... RO
............................................ RO
the
PCI configuration space of the VT82C686B.
function 5
The PCI configuration registers for the
are
Modem Codec
(00h)
Offset E - Header Type
(00h)
located in the
PCI configuration space. The I/O
function 6
registers are located in the system I/O space.
Offset F - BIST
......................................................... RO
Offset 13-10 - Base Address 0 – SGD Control / Status .. RW
PCI Configuration Space Header – Function 5 Audio
........................................always reads 0
.........................................default = 00h
31-16 Reserved
15-8 Base Address
Offset 1-0 - Vendor ID .......................................................RO
7-0 00000001b (256 bytes)
................. (1106h = VIA Technologies)
0-7 Vendor ID
Offset 3-2 - Device ID.........................................................RO
(3058h = 82C686B Audio Codec)
Offset 5-4 - Command.......................................................RW
........................................ always reads 0
Offset 17-14 - Base Address 1 – FM NMI Status ........... RW
........................................always reads 0
.....................................default = 0000h
31-16 Reserved
15-2 Base Address
1-0 01b (4 bytes)
0-7 Device ID
15-10 Reserved
Offset 1B-18 - Base Address 2 – MIDI Port ................... RW
.......................................fixed at 0
Fast Back-to-Back
9
8
7
6
5
4
3
2
1
0
........................................always reads 0
.....................................default = 0330h
31-16 Reserved
15-2 Base Address
1-0 01b (4 bytes)
.............................................fixed at 0
SERR# Enable
........................................fixed at 0
Address Stepping
Parity Error Response
................................fixed at 0
.....................................fixed at 0
VGA Palette Snoop
Offset 1F-1C - Base Address 3 – Codec Register ShadowRW
...................fixed at 0
Memory Write and Invalidate
........................................always reads 0
.....................................default = 0000h
31-16 Reserved
15-2 Base Address
1-0 01b (4 bytes)
...........................fixed at 0
Special Cycle Monitoring
.................................................fixed at 0
Bus Master
.............................................fixed at 0
Memory Space
............................... default=0 (disabled)
I/O Space
Offset 2F-2C – Subsystem ID / Sub Vendor ID............. RO*
*This register is RW if function 5-6 Rx42[5] = 1
Offset 7-6 - Status...........................................................RWC
Offset 34 – Capture Pointer (C0h) ................................... RO
........................ always reads 0
.............................. default=0
...............................fixed at 0
...............................fixed at 0
...............................fixed at 0
15 Detected Parity Error
14 Signalled System Error
13 Received Master Abort
12 Received Target Abort
11 Signalled Target Abort
10-9 DEVSEL# Timing
00 Fast
Offset 3C - Interrupt Line................................................ RW
........................................always reads 0
7-4 Reserved
3-0 Audio Interrupt Routing
0000 Disable................................................... default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disable
01 Medium.................................................... fixed
10 Slow
11 Reserved
........................................fixed at 0
8
Data Parity Error
........................fixed at 0
7
Fast Back-to-Back Capable
........................................ always reads 0
.................................................fixed at 1
........................................ always reads 0
6-5 Reserved
4
PM 1.1
3-0 Reserved
(nnh)
Offset 8 - Revision ID
...............................................RO
7-0 Silicon Revision Code
10h Revision A
11h Revision B
12h Revision C
(03h)
Offset 3D - Interrupt Pin
......................................... RO
13h Revision D
14h Revision E
20h Revision H
(00h)
Offset 3E - Minimum Grant
Offset 3F - Minimum Latency
.................................... RO
(00h)
................................. RO
Revision 1.71 June 9, 2000
-106- Function 5 & 6 Registers - AC97 Audio & Modem Codecs
ETC [ ETC ]
