VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.22 Pulse Width Modulation Unit
Vs1005 has a PWM output which can be programmed to generate any pulse width within 256
xtal clock periods.
PWM Registers
Reg Type Reset Abbrev
Description
0xFED4
0xFED5
r/w
r/w
0
0
PWM_PULSE[7:0] PWM pulse width, 0 - 255 clock cycles
PWM_FRAME[7:0] PWM frame length, 2 - 255 clock cycles
PWM_FRAME[7:0] defines the pwm frame length. Values 0 and 1 are not allowed and they
place the unit in powerdown (output is zero). With frame values > 1 the pwm output is enabled
with rising edge at start of frame and falling edge at PWM_PULSE[7:0]. If PWM_PULSE is zero
the output is always zero. If PWM_PULSE > PWM_FRAME the output is always at logic high
state.
PWM unit generates interrupt request at the start of each frame.
In vs1005 power-up as the pwrbtn pin is high the pwm output generates an oscillation for
external powering circuitry. The oscillation reguires that there is an external pull-up resistor
connected to the pwm pin.
PWM start-up oscillator
Item Min Typical Max Description
Pull-up resistor
Start-up frequency
100k
370kHz
Value of external pull-up resistor
Start-up oscillation frequency
Version: 0.2, 2012-03-16
98
ETC [ ETC ]
