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VS1005 参数 Datasheet PDF下载

VS1005图片预览
型号: VS1005
PDF下载: 下载PDF文件 查看货源
内容描述: 此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品 [此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品]
分类和应用:
文件页数/大小: 104 页 / 1715 K
品牌: ETC [ ETC ]
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VS1005g Datasheet  
11 VS1005 DEBUGGER  
11 VS1005 Debugger  
VS1005 has a hardware debugger which uses common Joint Test Action Group (JTAG) inter-  
face. The JTAG pins are in hardware debug mode when the dbgmode pin is pulled high. This  
enables the JTAG pins to access Test Acess Port (TAP) controller and swithes clocks to debug  
mode.  
Vs1005 Hardware Debuger Pins  
Name  
Package pin Description  
tms  
tdi  
31 Test mode select  
32 Test data in  
tdo  
tck  
33 Test data out  
34 Test clock  
dbgreq  
dbgmode  
35 Debug interrupt  
61 JTAG debug mode enable  
Debug functions are controlled with JTAG DR (data) and IR (instruction) registers which can be  
written and read in predefined JTAG states. JTAG state machine is shown in Figure 21.  
Figure 21: JTAG state machine.  
TAP function is selected by writing a special 4-bit instruction to IR register. Additionally to debug  
functions, some common JTAG functions are supported.  
Version: 0.2, 2012-03-16  
100  
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