VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.14 Uart Peripheral
RS232 UART implements a serial interface using rs232 standard.
Start
bit
Stop
bit
D0
D4
D1
D2
D3
D5
D6
D7
Figure 16: RS232 Serial Interface Protocol
When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission
begins with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a
stop bit (logic high). 10 bits are sent for each 8-bit byte frame.
10.14.1 Uart Peripheral Registers
UART Registers
Reg Type Reset Abbrev
Description
UART_STATUS[3:0] Status
UART_DATA[7:0] Data
UART_DATAH[15:8] Data High
UART_DIV Divider
0xFE00
0xFE01
0xFE02
0xFE03
r
0
0
0
0
r/w
r/w
r/w
UART_STATUS register monitors the uart status.
UART_STATUS Bits
Bits Description
Name
UART_ST_FRAMERR
UART_ST_RXORUN
UART_ST_RXFULL
UART_ST_TXFULL
UART_ST_TXRUNNING
4
3
2
1
0
Framing Error (stop bit was 0)
Receiver overrun
Receiver data register full
Transmitter data register full
Transmitter running
UART_ST_FRAMERR is set at the time of stop bit reception. When reception is functioning
normally, stop bit is always “1”. If, however, “0” is detected at the line input at the stop bit
time, UART_ST_FRAMERR is set to “1”. This can be used to detect “break” condition in some
protocols.
UART_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from
the receiver shift register to the data register, otherwise it is cleared.
UART_ST_RXFULL is set if there is unread data in the data register.
UART_ST_TXFULL is set if a write to the data register is not allowed (data register full).
UART_ST_TXRUNNING is set if the transmitter shift register is in operation.
UART_DATA is the uart data register. A read from UART_DATA returns the received byte in bits
7:0, bits 15:8 are returned as ’0’. If there is no more data to be read, the receiver data register
Version: 0.2, 2012-03-16
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