VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
SP_RS1_RV is the validity bit of the right channel sample word. If the audio sample word is not
a linear PCM, this bit must be set.
SP_LS1_LU is a user data bit for the left channel. Default value is ’0’. User data bits can be
used to convey an application specific message to the receiver. Some equipment categories
dictate the message, see IEC 60958-3.
SP_LS1_LV is the validity bit of the left channel sample word. If the audio sample word is not a
linear PCM, this bit must be set.
SP_CH2_FSO defines the original sampling frequency of the audio stream. “0000” means the
original sampling frequency is not indicated (default).
In SP_CH2_WRDL, the sample word length is coded with respect to SP_CH2_WRDLM. “000”
means the word length is not indicated.
SP_CH2_WRDLM indicates whether the maximum word length is 24 bits (’1’) or 20 bits (’0’).
S/PDIF TX Configuration SP_CFG
Name
Bits Description
SP_CFG_CLKDIV
SP_CFG_IE
SP_CFG_SND
15:2 Clock divider
1
0
Interrupt enable
Send words
SP_CFG_CLKDIV contains a clock divider value that is used to generate S/PDIF Transmit-
ter operating frequency. The target is twice the bit rate. Bit rate is sampling frequency of
the transmitted signal multiplied by 64. For example, 48 kHz audio signal requires bit rate of
3.072 MHz and consequent clock frequency for the peripheral is 6.144 MHz. Default value for
SP_CFG_CLKDIV is 4, resulting to Fs = 48 kHz when master clock frequency is 24.576 MHz.
Zero is forbidden value.
S/PDIF Transmitter frequencies
Fs
bit rate (Fs x 64) Target frequency for clock divider
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
2.048 MHz
2.8224 MHz
3.072 MHz
6.144 MHz
12.288 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
12.288 MHz
24.576 MHz
Divider = Master clock / Targer frequency, Divider = Master clock / (Fs * 64 * 2).
SP_CFG_IE, when ’1’, enables processor interrupt request when new values must be written
for the sample word registers: SP_TX_LDATA and SP_TX_RDATA. Default is ’0’.
SP_CFG_SND, when ’1’, S/PDIF Transmitter sends the data in the sample word registers.
Otherwise only empty subframes with zero payload will be sent. This is because the receiver
may use S/PDIF signal as a clock source and hence, the S/PDIF signal must not stop even
though no data is sent.
The S/PDIF Transmitter has one interrupt. Interrupt request is issued when SP_ST_NWRQ is
set, i.e. when new sample words must be written to the sample word registers.
Version: 0.2, 2012-03-16
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ETC [ ETC ]
