VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.15 Watchdog Peripheral
The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is
inactive. The counter reload value can be set by writing to WDOG_CONFIG. The watchdog is
activated by writing 0x4ea9 to register WDOG_RESET. Every time this is done, the watchdog
counter is reset. Every 65536’th clock cycle the counter is decremented by one. If the counter
underflows, it will activate vsdsp’s internal reset sequence.
Thus, after the first 0x4ea9 write to WDOG_RESET, subsequent writes to the same register
with the same value must be made no less than every 65536×WDOG_CONFIG clock cycles.
Once started, the watchdog cannot be turned off. Also, a write to WDOG_CONFIG doesn’t
change the counter reload value.
After watchdog has been activated, any read/write operation from/to WDOG_CONFIG or WDOG_DUMMY
will invalidate the next write operation to WDOG_RESET. This will prevent runaway loops from
resetting the counter, even if they do happen to write the correct number. Writing a wrong value
to WDOG_RESET will also invalidate the next write to WDOG_RESET.
Reads from watchdog registers return undefined values.
10.15.1 Watchdog Registers
Watchdog Registers
Reg Type Reset Abbrev
Description
0xFE20
0xFE21
0xFE22
w
w
w
0
0
0
WDOG_CONFIG
WDOG_RESET
WDOG_DUMMY[-] Dummy register
Configuration
Clock configuration
Version: 0.2, 2012-03-16
81
ETC [ ETC ]
