VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
full indicator will be cleared.
A receive interrupt will be generated when a byte is moved from the receiver shift register to
the receiver data register.
A write to UART_DATA sets a byte for transmission. The data is taken from bits 7:0, other
bits in the written value are ignored. If the transmitter is idle, the byte is immediately moved
to the transmitter shift register, a transmit interrupt request is generated, and transmission is
started. If the transmitter is busy, the UART_ST_TXFULL will be set and the byte remains in the
transmitter data register until the previous byte has been sent and transmission can proceed.
UART_DATAH is the same register as the UART_DATA, except that bits 15:8 are used.
UART_DIV register configures uart tansmission speed.
UART_DIV Bits
Name
Bits Description
UART_DIV_D1
UART_DIV_D2
15:8 Divider 1 (0..255)
7:0 Divider 2 (6..255)
The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending
on the master clock frequency to get the correct bit speed. The second divider (D2) must be
from 6 to 255.
fm
(D1+1)×(D2)
The communication speed f =
in bps.
, where fm is the XTAL, and f is the TX/RX speed
Version: 0.2, 2012-03-16
80
ETC [ ETC ]
