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VS1005 参数 Datasheet PDF下载

VS1005图片预览
型号: VS1005
PDF下载: 下载PDF文件 查看货源
内容描述: 此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品 [此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品]
分类和应用:
文件页数/大小: 104 页 / 1715 K
品牌: ETC [ ETC ]
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VS1005g Datasheet  
10 VS1005 PERIPHERALS AND REGISTERS  
The speed of the S/PDIF transmitter depends on the sampling frequency of the audio signal.  
Since S/PDIF signal is often used to retrieve a clock signal at the receiving end, S/PDIF trans-  
mitter must produce an exact frequency with a very low jitter.  
Supported sampling frequencies are 32 kHz, 48 kHz, 96 kHz and 192 kHz when master clock  
frequency is n x 12.288MHz. 44.1 kHz sampling frequency is supported.  
10.13.4 S/PDIF Transmitter Registers  
S/PDIF supports audio sample width of 16 to 24 bits. The exact figure is conveyed to the  
receiver by channel status bits. If the the transmitted sample word is less than 24 bits wide, the  
remaining LSB’s must be zero.  
Channel status registers provide interface to the S/PDIF standard implementation channel sta-  
tus bits. The S/PDIF Transmitter inserts the corresponding bits to their proper places in the  
transfer frame. Channel status data (byte 23) for cyclic redundancy check character (CRCC) is  
not tested yet.  
This document offers a terse description of the channel status bits. Full coverage in IEC 60958-  
3 is mandatory. Current implementation shares Channel Status Data bits (registers CHS0 and  
CHS1) for both channels!  
S/PDIF Transmitter Registers  
Reg Type Reset Abbrev  
Description  
SP_TX_LDATA_LSB Left channel Audio sample bits 7-0  
SP_TX_LDATA Left channel Audio sample bits 23-8  
SP_TX_RDATA_LSB Right channel Audio bits sample 7-0  
0xFD02  
0xFD03  
0xFD04  
0xFD05  
0xFD08  
0xFD09  
0xFD0A  
0xFD0B  
w
w
w
0
0
0
0
0
0
0
w
SP_TX_RDATA  
SP_TX_CHST0  
SP_TX_CHST1  
SP_TX_CHST2  
Right channel Audio sample bits 23-8  
Channel Status 0  
Channel Status 1  
r/w  
r/w  
r/w  
r/w  
Channel Status 1  
0x40 SP_TX_CFG  
Transmitter configuration  
SP_TX_LDATA, SP_TX_LDATA_LSB, SP_TX_RDATA and SP_TX_RDATA_LSB registers are  
transmitter data registers. S/PDIF data is 24 bits and it is divided in two registers. 16 MSB bits  
are in registers SP_TX_LDATA and SP_TX_RDATA. The remaining 8 LSB bits are in registers  
SP_TX_LDATA_LSB and SP_TX_RDATA_LSB.  
Channel Status SP_TX_CHST0  
Name  
Bits of data Bits of Chan- Description  
word  
nel status  
SP_CH0_CAT  
SP_CH0_MD0  
SP_CH0_PCMM  
SP_CH0_CP  
15:8  
7:6  
5:3  
2
15:8  
7:6  
5:3  
2
Category Code  
PCM Mode 0  
Linear PCM Mode  
Copyright  
SP_CH0_PCM  
SP_CH0_PROCON  
1
0
1
0
Linear PCM  
Professional/Consumer  
mode  
SP_CH0_CAT indicates to which category the device belongs. Default value is “00000000”.  
Version: 0.2, 2012-03-16  
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