VS1005g Datasheet
10
VS1005 PERIPHERALS AND REGISTERS
10.13
S/PDIF Peripheral
10.13.1 S/PDIF Receiver
S/PDIF receiver interface offers a receiver function for serial digital audio. S/PDIF supports
two channels which are multiplexed in one signal line. Synchronizing to S/PDIF input data bit
frequency is done by the digital frequency divider the clock of which is generated by the low
jitter programmable PLL. Supported sampling frequencies are 32.0 kHz, 44.1 kHz, 48.0 kHz,
96.0 kHz and 192.0 kHz.
S/Pdif Receiver peripheral device supports linear PCM sample recovery up to 24 bits, S/PDIF
subframe parity check, biphase channel coding check, subframe, frame, and block integrity
checks, and read miss notification. This version does not perform cyclic redundancy check
(CRC) for channel status bits in hardware. CRC check can be implemented by software if
needed.
Frame format is depicted in Figure 14. X, Y, and Z are the allowed preambles of a subframe.
An X subframe and an Y subframe constitute a frame. X preamble is replaced by Z preamble
every 192 frames to indicate block limit.
PR
EL
IM
Version: 0.2, 2012-03-16
Figure 14: S/PDIF Frame Format.
Subframe format is depicted in Figure 15. A Preamble is a signal pattern lasting 4 time slots.
S/Pdif Receiver decodes it and keeps track of frame and block integrity. A payload is max 24-
bit sample word. Validity bit indicates whether the payload is valid audio sample. User data
bit allows simultaneous data send. Channel information is conveyed in channel status bits as
specified in IEC 60958-1 and IEC 60958-3. S/Pdif Receiver peripheral device uses the parity
bit to calculate parity check. The result is shown in SP_CTL register bits LPerr and RPerr. Each
bit occupies one time slot of the subframe.
Figure 15: S/PDIF Sub-Frame Format.
IN
AR
72
Y
ETC [ ETC ]
