VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.12 Interruptable General purpose IO ports 0-2
Vs1005 has 3 general purpose IO ports that can operate either in GP mode or in perip mode.
In order to use pins as gpio the GPMODEx registers must be reset (default value).
GPIO port 0, 1 and register offsets are 0xFCA0, 0xFCC0 and 0xFCE0 accordingly. GPIO port
0 and 1 are 16-bits wide and GPIO port 2 is 14-bits wide.
Interruptable General I/O Registers, Prefix GPIOx_
Reg Type Reset Abbrev
Description
0
1
2
3
4
5
r/w
r/w
r
r/w
r/w
r/w
0
0
0
0
0
0
DDR
ODATA
IDATA
INT_FALL
INT_RISE
INT_PEND
Data direction
Data output
Data input (I/O pin state)
Falling edge interrupt enable
Rising edge interrupt enable
Interrupt pending source
6
7
8
9
w
w
r/w
r/w
r/w
0
0
0
0
0
SET_MASK
Data set (→ 1) mask
CLEAR_MASK Data clear (→ 0) mask
BIT_CONF
BIT_ENG0
BIT_ENG1
Bit engine config 0 and 1
Bit engine 0 read/write
Bit engine 1 read/write
10
GPIOx_DDR register configure the directions of each of the 16 I/O pins. A bit set to 1 in the
DDR turns the corresponding I/O pin to output mode, while a bit set to 0 sets the pin to input
mode. The register is set to all zeros in reset, i.e. all pins are inputs by default. The current
state of the DDR can also be read.
GPIOx_ODATA register sets the GPIO pin high or low. Only pins that are configured as outputs
are affected.
GPIOx_IDATA monitiors the current state of a pin. The actual logical levels of the I/O pins are
seen in the input data register. Note: The pin state can be read even if the pin is in peripheral
mode (i.e. GPMODEx[y] is set).
GPIOx_INT_RISE and GPIOx_INT_FALL configures an interrupt trigger edge. If a bit of the
falling edge interrupt enable register (GPIOx_INT_FALL) is set to 1, a falling edge in the cor-
responding pin (even when configured as output) will set the corresponding bit in the interrupt
pending source register (GPIOx_INT_PEND).
If a bit of the rising edge interrupt enable register (GPIOx_INT_RISE) is set to 1, a rising edge
in the corresponding pin (even when configured as output) will set the corresponding bit in the
interrupt pending source register (GPIOx_INT_PEND).
GPIOx_INT_PEND defines the source of a pending interrupt. If any of the bits in the interrupt
pending source register (GPIOx_INT_PEND) are set, an interrupt request is generated. Bits in
GPIOx_INT_PEND can be cleared by writing a 1-bit to the bit that is to be cleared.
Note: the interrupt request will remain asserted until all GPIOx_INT_PEND bits are cleared.
GPIOx_SET_MASK register can be used to mask GPIO pins high when GPIOx_ODATA register
is written. All bits that are set in the mask register also set the corresponding bit in the data
output register. Other bits retain their old values.
Version: 0.2, 2012-03-16
70
ETC [ ETC ]
