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VS1005 参数 Datasheet PDF下载

VS1005图片预览
型号: VS1005
PDF下载: 下载PDF文件 查看货源
内容描述: 此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品 [此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品]
分类和应用:
文件页数/大小: 104 页 / 1715 K
品牌: ETC [ ETC ]
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VS1005g Datasheet
10
VS1005 PERIPHERALS AND REGISTERS
When the DSP has written a packet into the transmit buffer, that is ready to be transmitted
to the PC by an endpoint, the DSP signals the USB firmware by setting the value of the
USB_EP_SENDn register of the endpoint that should transmit the packet (USB_EP_SEND0
for endpoint 0, USB_EP_SEND1 for endpoint 1 etc).
USB_EP_STn Bits
Name
Bits Description
EPnOUT (PC
Device) endpoint (0 .. 3) flags
USB_EP_STn_OTYP
15:14 00=bulk 01=interrupt 11=isochronous
USB_EP_STn_OENA
14:13 1=enabled 0=disabled
USB_EP_STn_OSTL
12 Force STALL
USB_EP_STn_OSTL_SENT
11 At least 1 STALL sent
reserved
10:8 Use ’0’
EPnIN (Device
PC) endpoint (0 .. 3) flags
USB_EP_STn_ITYP
7:6 00=bulk 01=interrupt 11=isochronous
USB_EP_STn_IENA
5 1=enabled 0=disabled
USB_EP_STn_ISTL
4 Force STALL
USB_EP_STn_ISTL_SENT
3 At least 1 STALL sent
USB_EP_STn_INAKSENT
2 At least 1 NAK sent
USB_EP_STn_IXMIT_EMP
1 Transmitter empty
reserved
0 Use ’0’
PR
EL
IM
10.11.2 USB Clocking Modes
10.11.3 USB Host
USB host is capable of:
Send Start of Frame (SOF) packets
Send SETUP, IN and OUT packets
Schedule transfers within 1ms frames
Signal USB bus reset
Provide USB power management
Version: 0.2, 2012-03-16
USB usage requires a special clock setup. The core clock must be set to 60MHz. If only
Full Speed USB is used the 60MHz clock can be achieved byt placing the PLL to 5x clocking
mode and using 12.000MHz XTAL. When High Speed USB is used the core clock must also be
60MHz but this clock is generated with a PLL which can be programmed with fractional multi-
plier factors. The xtal oscillator frequencies of 12.000MHz or 12.288MHz are recommended in
this mode.
USB module can be configured as an USB host. In USB host mode the 1.5kOhm pull up
resistor in D+ pin is replaced with 15kOhm pull down resistors in in both the D+ and D- pins.
IN
AR
69
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