VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
GPIOx_CLEAR_MASK register can be used to mask GPIO pins low when GPIOx_ODATA reg-
ister is written. All bits that are set in the mask clear the corresponding bit in the data output
register. Other bits retain their old values.
GPIOx_BIT_CONF is a bit engine configuration register and selects a mapping between an I/O
bit and a data output/input register bit for each of the bit engine registers.
GPIOx_BIT_CONF Bits
Name
Bits Description
GPIOx_BE_DAT1
GPIOx_BE_IO1
15:12 Data bit selection (0..15) for bit engine 1
11:8 I/O bit selection (0..15) for bit engine 1
GPIOx_BE_DAT0
GPIOx_BE_IO0
7:4 Data bit selection (0..15) for bit engine 0
3:0 I/O bit selection (0..15) for bit engine 0
GPIOx_BIT_ENG0 is a register used to read/write a GPIO pin specified in GPIOx_BIT_CONF
register.
When writing a value to the bit engine 0 register, the data bit specified in the configuration
register is copied to the data output register bit specified in the same register.
When reading a value from the bit engine 0 register, the data input register bit specified in the
configuration register is copied to the data bit specified in the same register, other bits read out
as 0.
GPIOx_BIT_ENG1 works just like GPIOx_BIT_ENG0.
Version: 0.2, 2012-03-16
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ETC [ ETC ]
