VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.13.2 S/PDIF Receiver Registers
The base address for S/Pdif Receiver interface registers is Y:0xFD00.
S/Pdif Receiver Registers
Address Type Reset
Abbrev
Description
0xFD00
0xFD01
0xFD02
0xFD03
0xFD04
0xFD05
0xFD06
0xFD07
r/w
r/w
r
r
r
0x1FF0 SP_RX_CF
S/PDif control and status register
S/PDif receiver clock divider register
0
0
0
0
0
0
0
SP_RX_CKDIV
SP_RX_LDATA_LSB S/PDif input left input channel, bits 8-0
SP_RX_LDATA
SP_RX_RDATA_LSB S/PDif left input channel, bits 8-0
SP_RX_RDATA
SP_RX_STAT
SP_RX_BLFRCNT
S/PDif left input channel, bits 23-8
r
S/PDif right input channel, bits 23-8
S/PDif status register
S/PDif frame status register
r/w
r
SP_RX_CF Bits
Bits Description
Name
SP_RX_CTL_EN
SP_RX_CTL_INTEN
3
1
S/Pdif enable
Interrupt enable
SP_RX_CTL_EN Enables S/Pdif Receiver peripheral. If disabled, i.e. ’0’, most of the peripheral
is resetted and synchronisation to S/PDIF stream is lost and must be re-acquired after enabling.
SP_RX_CKDIV Bits
Name
Bits Description
SP_RX_CKDIV
7:0 Receiver clock divider
SP_RX_CKDIV is an 8-bit clock divider value that is used to adjust the S/Pdif Receiver periph-
eral to proper Fs according to master clock frequency. Default value is 8, resulting to Fs = 48
kHz with master clock = 24.576 MHz. Values smaller than 4 are not allowed, since at least 4
samples per audio sample are needed (2 samples per biphase mark).
S/Pdif Receiver peripheral supports audio sampling frequencies up to 192 kHz.
The supported frequencies and corresponding bit rates are summarized in the following table.
Bit rate is sampling frequency multiplied by 64, which is channel number (2) times subframe
time slot count (32).
While the divider value should be targeted to bit rate of the table below, the peripheral actually
operates with quadruple clock rate. This must be accounted for in the system clocking design.
The system clock must be at least four (4) times the bit rate if S/PDIF peripheral is to be used.
In other words, SP_CTL_DIV values less than four ( < 4 ) are forbidden. Divider must be even
number.
Version: 0.2, 2012-03-16
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