EAGLE
PRELIMINARY
Ver 1.3
Control flag of Descriptor
The Control flag which records the descriptor information is read by the DMA controller and written to GDMACON. As
such, the role of Flags is identical to the GDMACON’s flag. However, if the state flag which indicates the DMA controller
status does not exist, existing bit 31 and 30 shall indicate the validity of next descriptor. The DMA controller finds the next
descriptor either by referring to the current descriptor at the end of data transfer or bit 31 of Control flag is referred if
configured as Chain mode. The DMA will attempt to read the next Descriptor if bit 31 is set to ‘1’. However, a ‘0’ value
represents that the current descriptor is considered as the last descriptor and an interrupt is requested to terminate the DMA
operation. Bit 30 allows interrupt generations when descriptors are read. (Other fields are identical to GDMACON)
This table shows the Description of Control flag when DMA controller is in Chain mode.
Bit
Description
31
Next Descriptor Flag
0: Enable next descriptor 1: Disable next descriptor
30
Descriptor Read Interrupt Mask
0: Disable Interrupt Mask
Reserved
Run DMA Operation
0 : Cancels DMA Operation
1 : Starts DMA Operation by S/W
Reserved
1: Enable interrupt Mask
29 : 25
24
23 : 19
18 : 16
Channel 0
Channel 1
DMA Request Source Selection
000 : External DREQx0
001 : I2S (CH0)
010 : SPI DREQx
011 : Reserved
DMA Request Source Selection
000 : External DREQx1
001 : NAND Flash RX DREQx
010 : SDC(SD Host Controller) DREQx
011 : Reserved
100 : Reserved
1xx : DMA Channel 1 (SW)
101 : NAND Flash TX DREQx
11x : DMA Channel0 (SW)
Active DMA Chain Mode
0 : Direct Mode 1 : Chain Mode
Protection and access information
bit 12 : Privileged or User
bit 13 : Bufferable or not bufferable
bit 14 : Cacheable or not cacheable
Lock
15
14 : 12
11
10
0: Unlock 1 : Lock
DMA Transfer Count Mode
0 : Reference Count
1 : not used (unlimited transfer)
9 : 8
DMA Burst Size
00 : No burst
01 : 4 beat incrementing burst
10 : 8 beat incrementing burst
11 : 16 beat incrementing burst
Direction of DMA Source Address
7 : 6
5 : 4
00 : Fixed Address
10 : Increment
01 : Reserved
11 : Decrement
Direction of DMA Destination Address
00 : Fixed Address
10 : Increment
01 : Reserved
11 : Decrement
3 : 2
1 : 0
Data Size for Transfer
00 : 8bit
01 : 16bit
10 : 32bit
11 : Reserved
Reserved
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
64
ETC [ ETC ]
